S12FTS128KV1 Datasheet, PDF (21/46 Pages) Freescale Semiconductor, Inc – 128k byte Flash (Non-Volatile) Memory

Freescale Semiconductor, In_Blc_oc._{k Guide — FTS128K V01.03}
3.3.1 FCLKDIV — Flash Clock Divider Register
The FCLKDIV register is used to control timed events in program and erase algorithms. This register is
unbanked.
Register address BASE + $100
R
W
RESET:
7
FDIVLD
0
6
PRDIV8
0
5
FDIV5
0
4
FDIV4
0
3
FDIV3
0
2
FDIV2
0
1
FDIV1
0
= Unimplemented or Reserved
Figure 3-2 Flash Clock Divider Register (FCLKDIV)
0
FDIV0
0
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
FDIVLD — Clock Divider Loaded.
1 = Register has been written to since the last reset.
0 = Register has not been written.
PRDIV8 — Enable Prescaler by 8.
1 = Enables a prescaler by 8, to divide the Flash module input oscillator clock before feeding into
the CLKDIV divider.
0 = The input oscillator clock is directly fed into the FCLKDIV divider.
FDIV[5:0] — Clock Divider Bits.
The combination of PRDIV8 and FDIV[5:0] effectively divides the Flash module input oscillator
clock down to a frequency of 150kHz - 200kHz. The maximum divide ratio is 512. Please refer to
section 4.1.1 for more information.
3.3.2 FSEC — Flash Security Register
This FSEC register holds all bits associated with the device security. This register is unbanked.
Register address BASE + $101
7
6
5
4
3
R
KEYEN
NV6
NV5
NV4
NV3
W
Reset: F
F
F
F
F
= Unimplemented or Reserved
2
1
0
NV2
SEC1
SEC0
F
F
F
21
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