S12FTS128KV1 Datasheet, PDF (20/46 Pages) Freescale Semiconductor, Inc – 128k byte Flash (Non-Volatile) Memory

Block Guide — FTS128K V01.0^F3^{reescale Semiconductor, Inc.}
The Flash module has hardware interlocks which protect data from accidental corruption. One protected
sector is located at the higher address end of Flash block 0, just below $FFFF. Another protected sector is
located at the lower address end of Flash block 0, just after the beginning of the Flash code implementation
at address $4000. Both the high and low address protected sectors in the Flash can be sized from 512 bytes
to 4K bytes. The middle Flash page can also exhibit protectable areas as indicated in the memory map
summary Table 3-2.
The NVM module also contains a set of 16 control and status registers located in address space BASE +
$100 to BASE + $10F. In order to accommodate two Flash blocks with a minimum register address space,
a set of registers (BASE+$104 to BASE+$10B) is duplicated in two banks. The active bank is selected by
the BKSEL bit in the unbanked Flash Configuration Register (FCNFG). A summary of these registers is
given in Table 3-3.
Table 3-3 FTS128K Memory Map
Address
Offset
Use
$_00
Flash Clock Divider Register (FCLKDIV)
$_01
Flash Security Register (FSEC)
$_02
Flash Test Mode Register (FTSTMOD)¹
$_03
Flash Configuration Register (FCNFG)
$_04
Flash Protection Register (FPROT)
$_05
Flash Status Register (FSTAT)
$_06
Flash Command Register (FCMD)
$_07
RESERVED1²
$_08
16-bit Address Register (FADDRHI)³
$_09
16-bit Address Register (FADDRLO)⁴
$_0A
16-bit Data Register (FDATAHI)⁵
$_0B
16-bit Data Register (FDATALO)⁶
NOTES:
1. Intended for factory test purposes only.
2. RESERVED1 intended for factory test purposes only.
3. Intended for factory test purposes only.
4. Intended for factory test purposes only.
5. Intended for factory test purposes only.
6. Intended for factory test purposes only.
Access
R/W
R
R
R/W
R/W
R/W
R/W
R
R
R
R
R
NOTE: Register Address = Base Address + Address Offset, where the Base Address is
defined at the MCU level and the Address Offset is defined at the module level.
3.3 Register Descriptions
NOTE
20
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