S12FTS128KV1 Datasheet, PDF (34/46 Pages) Freescale Semiconductor, Inc – 128k byte Flash (Non-Volatile) Memory

Block Guide — FTS128K V01.0^F3^{reescale Semiconductor, Inc.}
4.1.2 Program and Erase Sequences in User Mode
A Command State Machine is used to supervise the write sequencing for program and erase. The
erase-verify command follows the same flow. Before starting a command sequence, it is necessary to
verify that there is no pending access error or protection violation in either of the Flash blocks (the
ACCERR and PVIOL flags should be cleared in the FSTAT registers) It is then required to set the PPAGE
register, as well as to set the Flash configuration register FCNFG. The procedure is as follows:
1. Verify that all ACCERR and PVIOL flags in the FSTAT register are cleared in both banks. This
requires to check the FSTAT content for both conditions of the BKSEL bit in the FCNFG register.
1. Write to bit BKSEL in the FCNFG register to select the bank of registers corresponding to the Flash
block to be programmed or erased (see Table 3-5).
2. Write to the core PPAGE register ($x030) to select one of the pages to be programmed if
programming in the $8000-$BFFF address range. There is no need to set PPAGE when
programming in the $4000-$7FFF or $C000-$FFFF address ranges.
After this possible initialization step the CBEIF flag should be tested to ensure that the address, data and
command buffers are empty. If so, the program/erase command write sequence can be started. The
following 3-step command write sequence must be strictly adhered to and no intermediate writes to the
Flash module are permitted between the 3 steps. It is possible to read any Flash register during a command
sequence. The command sequence is as follows:
1. Write the aligned data word to be programmed to the valid Flash address space. The address and
data will be stored in internal buffers. For program, all address bits are valid. For erase, the value
of the data bytes is don’t care. For mass erase, the address can be anywhere in the available address
space of the block to be erased. For sector erase the address bits[8:0] are ignored for the Flash.
2. Write the program or erase command to the command buffer. These commands are listed in Table
4-1.
3. Clear the CBEIF flag by writing a “1” to it to launch the command. When the CBEIF flag is cleared,
the CCIF flag is cleared by hardware indicating that the command was successfully launched. The
CBEIF flag will be set again indicating the address, data and command buffers are ready for a new
command sequence to begin.
The completion of the command is indicated by the CCIF flag setting. The CCIF flag only sets when all
active and pending commands have been completed.
NOTE
The Command State Machine will flag errors in program or erase write sequences by means of the
ACCERR (access error) and PVIOL (protection violation) flags in the FSTAT register. An erroneous
command write sequence will abort and set the appropriate flag. If set, the user must clear the ACCERR
or PVIOL flags before commencing another command write sequence. By writing a 0 to the CBEIF flag
the command sequence can be aborted after the word write to the Flash address space or after writing a
command to the FCMD register and before the command is launched. Writing a “0” to the CBEIF flag in
this way will set the ACCERR flag.
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