908E624_10 Datasheet, PDF (36/40 Pages) Freescale Semiconductor, Inc – Integrated Triple High Side Switch with Embedded MCU and LIN Serial Communicationfor Relay Drivers

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
908E624
INTRODUCTION
This thermal addendum is provided as a supplement to the MM908E624
technical datasheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application, and packaging information is provided in the datasheet.
54-TERMINAL
SOICW
Packaging and Thermal Considerations
The MM908E624 is a dual die package. There are two heat sources in the
package independently heating with P₁ and P₂. This results in two junction
temperatures, T_J1 and T_J2, and a thermal resistance matrix with R_θJAmn.
For m, n = 1, R_θJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P₁.
For m = 1, n = 2, R_θJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P₂. This applies to
R_θJ21 and R_θJ22, respectively.
DWB SUFFIX
EW (Pb-FREE) SUFFIX
98ASA99294D
54-TERMINAL SOICW
T_J1
T_J2
=
R_θJA11 R_{θJA12 .} P₁
R_θJA21 R_θJA22
P₂
Note For package dimensions, refer to the
MM908E624 datasheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below
Standards
Table 16. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/ W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
R_θJAmn ⁽¹⁾⁽²⁾
40
31
36
R_θJBmn ⁽²⁾⁽³⁾
25
16
21
R_θJAmn ⁽¹⁾⁽⁴⁾
57
47
52
R_θJCmn ⁽⁵⁾
21
12
16
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
54 Terminal SOIC
0.65 mm Pitch
17.9 mm x 7.5 mm Body
908E624
36
Analog Integrated Circuit Device Data
Freescale Semiconductor