908E624_10 Datasheet, PDF (28/40 Pages) Freescale Semiconductor, Inc – Integrated Triple High Side Switch with Embedded MCU and LIN Serial Communicationfor Relay Drivers

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
908E624 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between the microcontroller and the analog die of the
908E624.
The interface consists of four terminals (see Figure 17):
• SS—Slave Select
• MOSI—Master-Out Slave-In
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The master sends 8 bits of control information and the slave
replies with 8 bits of status data.
SS
MOSI
Register write data
D7 D6 D5 D4 D3 D2 D1 D0
MISO
Register read data
D7 D6 D5 D4 D3 D2 D1 D0
SPSCK
Read data latch
Write data latch
Rising edge of SPSCK
Change MISO/MOSI Output
Falling edge of SPSCK
Sample MISO/MOSI Input
Figure 17. SPI Protocol
During the inactive phase of the SS (HIGH), the new data
transfer is prepared.
The data transfer is only valid if exactly 8 sample clock
edges are present in the active (low) phase of SS.
The falling edge of the SS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
With the rising edge of the SPI clock, SPSCK the data is
moved to MISO/MOSI terminals. With the falling edge of the
SPI clock SPSCK the data is sampled by the Receiver.
The rising edge of the slave select SS indicates the end of
the transfer and latches the write data (MOSI) into the
register The SS high forces MISO to the high impedance
state.
908E624
28
Analog Integrated Circuit Device Data
Freescale Semiconductor