908E624_10 Datasheet, PDF (12/40 Pages) Freescale Semiconductor, Inc – Integrated Triple High Side Switch with Embedded MCU and LIN Serial Communicationfor Relay Drivers

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP ≤ 16 V, - 40°C ≤ T_J ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T_A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER
Driver Characteristics for Normal Slew Rate ^{(17), (18)}
Dominant Propagation Delay TXD to LIN
Dominant Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Propagation Delay Symmetry: t _DOM-MIN - t _REC-MAX
Propagation Delay Symmetry: t _DOM-MAX - t _REC-MIN
Driver Characteristics for Slow Slew Rate ^{(17), (19)}
t _DOM-MIN
—
—
t _DOM-MAX
—
—
t _REC-MIN
—
—
t _REC-MAX
—
—
dt1
-10.44
—
dt2
—
—
50
μs
50
μs
50
μs
50
μs
—
μs
11
μs
Dominant Propagation Delay TXD to LIN
Dominant Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Propagation Delay Symmetry: t _DOM-MIN - t _REC-MAX
Propagation Delay Symmetry: t _DOM-MAX - t _REC-MIN
Driver Characteristics for Fast Slew Rate
t _DOM-MIN
—
—
100
μs
t _DOM-MAX
—
—
100
μs
t _REC-MIN
—
—
100
μs
t _REC-MAX
—
—
100
μs
dt1s
- 22
—
—
μs
dt2s
—
—
23
μs
LIN High Slew Rate (Programming Mode)
Receiver Characteristics and Wake-Up Timings
SR_FAST
—
15
—
V / μs
Receiver Dominant Propagation Delay ⁽²⁰⁾
Receiver Recessive Propagation Delay ⁽²⁰⁾
t _RL
—
3.5
6.0
μs
t _RH
—
3.5
6.0
μs
Receiver Propagation Delay Symmetry
t _R-SYM
- 2.0
—
2.0
μs
Bus Wake-Up Deglitcher
Bus Wake-Up Event Reported ⁽²¹⁾
t _PROPWL
35
t _WAKE
—
—
150
μs
20
—
μs
Notes
17. V_SUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
18. See Figure 6, page 15.
19. See Figure 7, page 16.
20. Measured between LIN signal threshold V_IL or V_IH and 50% of RXD signal.
21. t_WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the V_DD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
908E624
12
Analog Integrated Circuit Device Data
Freescale Semiconductor