BC3770 Datasheet, PDF (26/45 Pages) Freescale Semiconductor, Inc – 2.0 A Switch-Mode Charger

5.5.2 Writing to Control Registers
To write to device control registers, the master needs to initiate a communication link by first generating a START condition on the I²C
bus. The master then sends the Write address. If the address matches to device’s Write address, the device sends an acknowledge bit
to the master. Next, the master sends the control register address. If device receives a valid I²C control register address, it returns an
acknowledge bit. Following this, the master sends a byte of data to be written. The device receives this byte of data and sends an
acknowledge bit back to master. The internal control register is updated right after an acknowledge bit is sent to master. If all the control
registers need to be updated at once, there is no need to repeat the device and register address. The register address is incremented in
the I²C block right after the acknowledge bit. Therefore, all the control registers’ byte data can be updated serially at once. The write data
format in single packet is shown in Figure 16 and Figure 17.
7-bit
Sub Address 8-bit
8-bit
S
SLAVE ADDRESS
W
ACK CONTROL REGISTER ADDRESS ACK Data to the Control Register ACK Data to the Control Register ACK Data to the Control Register ACK Data to the Control Register ACK
P
Start
Write:0
Register Address 7-bit
MSB:0
Figure 16. Repeated Data Write to a Single Register
Master
Slave
7-bit
S
SLAVE ADDRESS
Sub Address 8-bit
8-bit
W
ACK CONTROL REGISTER ADDRESS
ACK
Data to the Control Register
K
ACK
Data to the Control
Register K+1
ACK
Data to the Control
Register K+2
Start
Write:0
K Register Address 7-bit
MSB:1
Figure 17. Burst Data Write to Multiple Registers
ACK
Data to the Control
Register K+N-1
Note: A single byte read is initiated by the master with P immediately following the first data byte.
ACK
P
Master
Slave
5.5.3 Reading to Control Registers
To read from device registers, the master has to generate a START condition. The master then must supply the device Write address. If
this address matches the device Write address, an acknowledge bit is sent to master. Following this, the master sends the register address
from which the master wants to read data. If the register address is valid, an acknowledge bit is returned to master. The master then sends
a repeated START condition followed by device Read address. The device sends an acknowledge bit if the Read address is valid. Next,
the device I²C sends a byte of data from the previously received register address. If the master acknowledges, then the register address
in the device is incremented by one and the data from this register is sent to master again. Therefore, multiple registers can be read without
sending repeated device and register addresses to device. If the master does not acknowledge or sends a STOP condition, the Read
cycle is terminated. The device supports combined mode and split mode as shown in Figures 18 to 21.
7-bit
Sub Address 8-bit
7-bit
8-bit
8-bit
S
SLAVE ADDRESS
W
ACK CONTROL REGISTER ADDRESS ACK
Sr
SLAVE ADDRESS
RR
ACK
READ DATA 1
from the specified address
ACK
….
READ DATA N
from the same specified address
NA
P
Register Address 7-bit
Start
Write:0 MSB:0
Re-Start
Read:1
NACK Stop
Figure 18. Repeated Data Read from a Single Register- Combined Mode
Note: A single byte read is initiated by the master with P immediately following first data byte.
Master
Slave
7-bit
Sub Address 8-bit
7-bit
8-bit
8-bit
S
SLAVE ADDRESS
W
ACK CONTROL REGISTER ADDRESS ACK
Sr
SLAVE ADDRESS
RR
ACK
READ DATA 1
from the specified address
ACK
….
READ DATA N
from the same specified address+N
NA
P
Register Address 7-bit
Start
Write:0 MSB:1
Re-Start
Read:1
NACK Stop
Figure 19. Burst Data Read from Multiple Registers- Combined Mode
Note: A single byte read is initiated by the master with P immediately following first data byte.
Master
Slave
Analog Integrated Circuit Device Data
Freescale Semiconductor
BC3770
26