BC3770 Datasheet, PDF (25/45 Pages) Freescale Semiconductor, Inc – 2.0 A Switch-Mode Charger

5.5.1.4 Byte Format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte
has to be followed by an acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit
by servicing an internal interrupt, it can hold the clock line SCL Low to force the master into a wait state. Data transfer then continues when
the slave is ready for another byte of data and releases clock line SCL.
5.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge bit is used for handshaking purpose between the master and slave. The master and slave both can either receive or
send eight bits of serial data, depending on whether the master sends device’s read address or write address at the beginning of the data
transfer sequence. In either case, the receiver must send an acknowledge bit to the transmitter to complete transmission of one data byte
without any errors. When the device is written to, it acknowledges its write address as well as the following data bytes. When it is read
from, device only acknowledges its read address.
The device generates an acknowledge bit, right after receiving eight bits of data, by pulling SDA Low during the INTB clock pulse’s entire
High period. The master generates a similar acknowledge byte when it reads from device. The transmitter must let go of SDA during the
ninth clock cycle’s high period, to allow the receiver to generate an acknowledge bit. The generation of the acknowledge bit is shown in
Figure 15.
When SDA remains High during this 9th clock pulse, this is defined as the Not Acknowledge signal. The master can then generate either
a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. There are five conditions that lead to the
generation of a NACK:
1. No receiver is present on the bus with the transmitted address, so there is no device to respond with an acknowledge.
2. The receiver is unable to receive or transmit, because it is performing some real-time function and is not ready to start
communication with the master.
3. During the transfer the receiver gets data or commands it does not understand.
4. During the transfer, the receiver cannot receive any more data bytes.
5. A master-receiver needs to signal the end of the transfer to the slave transmitter.
DATA Output
by Master
Not acknowledge
DATA Output
by Slave
acknowledge
SCL
1
2
START
Condition
9
Clock for
acknowledgement
Figure 15. BUS Acknowledge Cycle
BC3770
25
Analog Integrated Circuit Device Data
Freescale Semiconductor