BC3770 Datasheet, PDF (22/45 Pages) Freescale Semiconductor, Inc – 2.0 A Switch-Mode Charger

5.3.10.5 Supplement Mode
When the VSYS voltage falls below the battery voltage while a valid input is attached, the Q4 FET turns On and the Q4 FET gate regulates
the gate drive of Q4 so the minimum VSYS stays at 50 mV below BATREG in the Supplement mode. This prevents oscillation from
entering and exiting Supplement mode. As the discharge current increases, the Q4 gate is regulated with a higher voltage, to reduce
R_DS(on) until Q4 is full conduction.
5.3.10.6 Charging Current Reduction in VSYS Overload
When the input current limit is detected in Charge mode by either a system overload or a programmed value is lower than the sum of load
current and charge current, the device reduces the charge current until the limited input current falls below the preset current limit
threshold, and the input voltage rises above the input voltage limit while maintaining the VSYS voltage at 3.4 V.
Although the charge current is reduced to 0 mA, the input power source is still overloaded, and the system voltage starts to drop. Once
the system voltage falls 50 mV below the battery voltage, the device automatically enters the Supplement mode and the battery starts
discharging so the system is supported from the both the input supply and battery. An corresponding interrupt for VSYS overload triggers
via the INTB pin.
5.4 Protection And Diagnosis Features
5.4.1 Input Overvoltage Protection
When the input voltage exceeds the overvoltage protection (OVP) threshold, internal switches immediately turn off and disconnect the
load and the charger from the power source, preventing damage to any downstream components. Simultaneously, the fault flag is
triggered, alerting the system. As soon as the OVP event stays over the deglitch time, t_{INPUT_OVP}, the converter resumes.
5.4.2 Battery (BAT) Overvoltage Protection
When the BATREG voltage exceeds the battery overvoltage protection threshold, V_{BAT_OVP} (typ. V_{BAT_REG}+ 0.1 V), the device turns off
the PWM converter and sets the fault status bit. Simultaneously, the fault flag is asserted, alerting the system. There is a 0.1 V hysteresis
in the internal threshold voltage. If the OVP event over the deglitch time is released, the converter and charging resume.
5.4.3 Reverse Blocking
In the reverse blocking mode (V_BUS - V_BATREG)  50 mV (typ.), charging is disabled and the device is entered into Charger-suspended
mode to minimize current drain from BATREG.
5.4.4 Thermal Regulation and Protection
When the device’s die temperature reaches T_CF (around 100 °C), the device reduces the charge current by around 3.33% of the fast-
charge current per °C. This drives the charge current down to 0 mA at 130 °C. Since the system load has priority over the battery charging,
the battery charge current is reduced to 0 mA before the input limiter drops the system load current. If the junction temperature rises
beyond 130 °C and then hits 150 °C, the PWM switcher shuts down to allow no input current from the input source. This prevents further
die heating. In this condition, the system output voltage is regulated at BATREG. This internal thermal protection helps to improve device
reliability. The device automatically goes back to normal operation when the die temperature cools down below 130 °C. In these thermal
regulation and shutdown modes, I²C access is still active.
Analog Integrated Circuit Device Data
Freescale Semiconductor
BC3770
22