BC3770 Datasheet, PDF (24/45 Pages) Freescale Semiconductor, Inc – 2.0 A Switch-Mode Charger

5.5 Logic Commands And Registers
5.5.1 Serial Interface
I²C is a two-wire serial interface developed by Phillips Semiconductor. The bus consists of a data line, SDA, and a clock line, SCL, with
pull-up structures. When the bus is idle, both the SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C
bus through open drain I/O pins, SDA, and SCL. A master generates the clock signal and device addresses. The master also generates
specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under
the master device.
The device works as a slave and is compatible with the following data transfer modes, as defined in the I²C-Bus Specification: Standard
mode (100 kbps) and Fast mode (400 kbps). The interface adds flexibility to all necessary control options of the program, and enables
most functions to be programmed to the new values, depending on the instantaneous application requirements. I²C is asynchronous,
which means that it runs off of SCL.The data transfer protocol for Standard and Fast modes is exactly the same.
5.5.1.1 Bus Speed
The device I²C interface supports bus SCL clock speeds up to 400 kbps for Full-speed mode. The SCL and SDA input buffers incorporate
spike suppression and Schmitt triggers to reject short glitches, as required by the I²C specifications.
5.5.1.2 Data Validity
During all transmissions, the master ensures the data is valid. A valid data condition requires the SDA line to be stable during the High
period of the clock (see Figure 13). The High or Low state of the data line can only change when the clock signal on the SCL line is Low
(see Figure 1). One clock pulse is generated for each data bit transferred.
SDA
SCL
Data Valid
Change
of data
allowed
Figure 13. Bit Transfer on the I²C Bus
5.5.1.3 Start and Stop Condition
All transactions begin with a START (S) and can be terminated by a STOP (P) (see Figure 2). A High to Low transition on the SDA line
while SCL is High defines a START condition. A Low to High transition on the SDA line while SCL is High defines a STOP condition.
SDA
SCL
START
STOP
Condition
Condition
Figure 14. START and STOP Conditions
START and STOP conditions are always generated by the master. The bus is considered to be busy after a START condition. The bus
is considered to be free again a certain time after the STOP condition.
Analog Integrated Circuit Device Data
Freescale Semiconductor
BC3770
24