33486A Datasheet, PDF (26/30 Pages) Freescale Semiconductor, Inc – Dual High-Side Switch for H-Bridge Applications

ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
33486A
DUAL HIGH-SIDE SWITCH FOR H-BRIDGE APPLICATIONS
Introduction
This thermal addendum is provided as a supplement to the MC33486
technical datasheet. The addendum provides thermal performance
information that may be critical in the design and development of
system applications. All electrical, application, and packaging
information is provided in the datasheet.
20-TERMINAL
HSOP
Packaging and Thermal Considerations
The MC33486A package is a dual die package. There are two heat
sources in the package independently heating with P₁ and P₂. This
results in two junction temperatures, T_J1 and T_J2, and a thermal
resistance matrix with R_θJAmn.
For m, n = 1, R_θJA11 is the thermal resistance from Junction 1 to the
reference temperature while only heat source 1 is heating with P₁.
For m = 1, n = 2, R_θJA12 is the thermal resistance from Junction 1 to
the reference temperature while heat source 2 is heating with P₂. This
applies to R_θJ21 and R_θJ22, respectively.
DH SUFFIX
98ASH70702A
20-TERMINAL HSOP
Note For package dimensions, refer to the
33486A device datasheet.
T_J1
T_J2
=
R_θJA11 R_{θJA12 .} P₁
R_θJA21 R_θJA22
P₂
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
Standards
Table 6. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
R_θJAmn⁽¹⁾⁽²⁾
19
18
21
R_θJBmn⁽²⁾⁽³⁾
7.0
6.0
10
R_θJAmn⁽¹⁾⁽⁴⁾
51
50
53
R_θJCmn⁽⁵⁾
< 0.5
0
3.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
20 Terminal HSOP-EP
1.27 mm Pitch
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Thermal vias
connected to top
buried plane
Figure 30. Thermal Land Pattern for Direct Thermal
Attachment per JESD51-5
33486A
26
Analog Integrated Circuit Device Data
Freescale Semiconductor