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MC9S08QD4 Datasheet, PDF (25/202 Pages) Freescale Semiconductor, Inc – Microcontrollers
Chapter 2 External Signal Description
2.2.5.2 Output Slew Rate Control
Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate
control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in
order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
2.2.5.3 Output Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in one of
the drive strength select registers (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
Table 2-1. Pin Sharing Priority
Lowest <- Pin Function Priority -> Highest
Port Pins
Alternative
Function
Alternative
Function
Alternative
Function
Reference1
PTA0
PTA1
PTA2
PTA3
PTA4
PTA52
KBI1P0
KBI1P1
KBI1P2
KBI1P3
TPM2CH0O
TPM2CH0I
TPM1CH0
TPM1CH1
TCLK1
TCLK2
BKGD/MS
IRQ
ADC1P03
ADC1P13
ADC1P23
ADC1P33
RESET
KBI1, ADC1, and TPM1 Chapters
KBI1, ADC1, and TPM1 Chapters
KBI1, ADC1, and TPM1 Chapters
KBI1, ADC1, and TPM2 Chapters
TPM2 Chapters
IRQ4, and TPM2 Chapters
1 See the module section listed for information on modules that share these pins.
2 Pin does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this
pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are
pulled to VDD.
3 If both of these analog modules are enabled both will have access to the pin.
4 See Section 5.8, “Reset, Interrupt, and System Control Registers and Control Bits,” for information on
configuring the IRQ module.
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
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