MC9S08AC60 Datasheet, PDF (181/348 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Internal Clock Generator (S08ICGV4)
Table 10-10. ICG Configuration Consideration
Clock Reference Source = Internal
Clock Reference Source = External
FLL
Engaged
FEI
4 MHz < f_Bus < 20 MHz.¹
Medium power (will be less than FEE if oscillator
range = high)
Good clock accuracy (After IRG is trimmed)
Lowest system cost (no external components
required)
IRG is on. DCO is on. ²
FEE
4 MHz < f_Bus < 20 MHz.¹
Medium power (will be less than FEI if oscillator
range = low)
High clock accuracy
Medium/High system cost (crystal, resonator or
external clock source required)
IRG is off. DCO is on.
FLL
Bypassed
SCM
This mode is mainly provided for quick and reliable
system startup.
3 MHz < f_Bus < 5 MHz (default).¹
3 MHz < f_Bus < 20 MHz (via filter bits).¹
Medium power
Poor accuracy.
IRG is off. DCO is on and open loop.
FBE
f_Bus range ≤ 8 MHz when crystal or resonator is
used.
Lowest power
Highest clock accuracy
Medium/High system cost (Crystal, resonator or
external clock source required)
IRG is off. DCO is off.
1 _{Range values are given for an assumed RFD = 1. Changing the RFD allows for a lower minimum frequency.}
2 _{The IRG typically consumes 100 μA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency.}
For minimum power consumption and minimum jitter, choose N and R to be as small as possible.
The following sections contain initialization examples for various configurations.
NOTE
Hexadecimal values designated by a preceding $, binary values designated
by a preceding %, and decimal values have no preceding character.
Important configuration information is repeated here for reference.
Table 10-11. ICGOUT Frequency Calculation Options
Clock Scheme
f_ICGOUT1
P
SCM — self-clocked mode (FLL bypassed
f_ICGDCLK / R
NA
internal)
FBE — FLL bypassed external
FEI — FLL engaged internal
FEE — FLL engaged external
f_ext / R
(f_IRG / 7)* 64 * N / R
f_ext * P * N / R
NA
64
Range = 0 ; P = 64
Range = 1; P = 1
1 _{Ensure that fICGDCLK, which is equal to fICGOUT * R, does not exceed fICGDCLKmax.}
Note
Typical f_ICGOUT = 8 MHz
immediately after reset
Typical f_IRG = 243 kHz
MFD Value
000
001
010
Table 10-12. MFD and RFD Decode Table
Multiplication Factor (N)
4
6
8
RFD
000
001
010
Division Factor (R)
÷1
÷2
÷4
MC9S08AC60 Series Data Sheet, Rev. 2
Freescale Semiconductor
181