MC9S08AC60 Datasheet, PDF (178/348 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Internal Clock Generator (S08ICGV4)
10.5.9 FLL Loss-of-Clock Detection
The reference clock and the DCO clock are monitored under different conditions (see Table 10-8).
Provided the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets
minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either
one falls below a certain frequency, f_LOR and f_LOD, respectively, the LOCS status bit will be set to indicate
the error. LOCS will remain set until it is acknowledged or until the MCU is reset. LOCS is cleared by
reading ICGS1 then writing 1 to ICGIF (LOCRE = 0), or by a loss-of-clock induced reset (LOCRE = 1),
or by any MCU reset.
If the ICG is in FEE, a loss of reference clock causes the ICG to enter SCM, and a loss of DCO clock causes
the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to
enter SCM. In each case, the CLKST and CLKS bits will be automatically changed to reflect the new state.
If the ICG is in FEE mode when a loss of clock occurs and the ERCS is still set to 1, then the CLKST bits
are set to 10 and the ICG reverts to FBE mode.
A loss of clock will also cause a loss of lock when in FEE or FEI modes. Because the method of clearing
the LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE = 1 and
LOCRE = 0. In this case, the interrupt would be overridden by the reset for the loss of lock.
Table 10-8. Clock Monitoring (When LOCD = 0)
Mode
CLKS REFST
ERCS
External Reference
Clock
Monitored?
DCO Clock
Monitored?
Off
0X or 11
X
Forced Low
No
No
10
0
Forced Low
10
1
Real-Time¹
SCM
0X
X
Forced Low
(CLKST = 00)
10
0
Forced High
10
1
Real-Time
11
X
Real-Time
No
Yes⁽¹⁾
No
No
Yes
Yes
No
No
Yes²
Yes⁽²⁾
Yes⁽²⁾
Yes⁽²⁾
FEI
0X
X
Forced Low
No
Yes
(CLKST = 01)
11
X
Real-Time
Yes
Yes
FBE
10
0
Forced High
No
No
(CLKST = 10)
10
1
Real-Time
Yes
No
FEE
11
X
Real-Time
Yes
Yes
(CLKST = 11)
1 _{If ENABLE is high (waiting for external crystal start-up after exiting stop).}
2 _{DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode.}
MC9S08AC60 Series Data Sheet, Rev. 2
178
Freescale Semiconductor