MC9S08AC60 Datasheet, PDF (130/348 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Cyclic Redundancy Check (S08CRCV1)
8.3 Register Definition
8.3.1 Memory Map
Table 8-1. CRC Register Summary
Name
CRCH
R
(offset=0) _W
CRCL
R
(offset=1) _W
7
Bit 15
Bit 7
6
Bit 14
Bit 6
5
Bit 13
Bit 5
4
Bit 12
Bit 4
3
Bit 11
Bit 3
2
Bit 10
Bit 2
1
Bit 9
Bit 1
0
Bit 8
Bit 0
8.3.2 Register Descriptions
The CRC module includes:
• A 16-bit CRC result and seed register (CRCH:CRCL)
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all CRC registers. This section refers to registers only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
8.3.2.1 CRC High Register (CRCH)
7
R
Bit 15
W
6
Bit 14
5
Bit 13
4
Bit 12
3
Bit 11
2
Bit 10
1
Bit 9
0
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 8-3. CRC High Register (CRCH)
Table 8-2. Register Field Descriptions
Field
Description
7:0
CRCH
CRCH — This is the high byte of the 16-bit CRC register. A write to CRCH will load the high byte of the initial 16-bit
seed value directly into bits 15-8 of the shift register in the CRC generator. The CRC generator will then expect the
low byte of the seed value to be written to CRCL and loaded directly into bits 7-0 of the shift register. Once both seed
bytes written to CRCH:CRCL have been loaded into the CRC generator, and a byte of data has been written to
CRCL, the shift register will begin shifting. A read of CRCH will read bits 15-8 of the current CRC calculation result
directly out of the shift register in the CRC generator.
MC9S08AC60 Series Data Sheet, Rev. 2
130
Freescale Semiconductor