33813 Datasheet, PDF (17/54 Pages) Freescale Semiconductor, Inc – One Cylinder Small Engine Control IC

Table 5. Dynamic Electrical Characteristics ⁽¹⁵⁾
Characteristics noted under conditions of 6.0 V  V_PWR  18 V, -40 C  T_C  125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V_PWR = 13 V, T_A = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
ALL LOW SIDE DRIVERS (CONTINUED)
Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)
t_PLH
• Input at 50%V_DD to Output voltage 10% of V_LOAD (INJ1, ROUT1, ROUT2,
LAMP)
µs
–
1.0
5.0
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50%V_DD to Output voltage 10% of V_LOAD (TACHOMETER)
Output Slew Rate, Tachout
• R_LOAD = 500 V_LOAD = 14 V
t_PLH
µs
–
1.0
6.0
t _SR(FALL)
V/s
6.0
–
14
ALL GATE PRE-DRIVER (IGN1 AND O2H)
Output OFF Open-circuit Fault Filter Timer
Over-current (short-circuit) Fault Filter Timer
Propagation Delay (Input Rising Edge OR CSB to Output Rising Edge)
• Input at 50%V_DD to Output voltage 10% of V_GS(ON)
Propagation Delay (Input Falling Edge OR CSB to Output Falling Edge)
• Input at 50%V_DD to Output voltage 90% of V_GS(ON)
SPI DIGITAL INTERFACE TIMING ⁽¹⁶⁾
t_(OFF)OC
µs
100
–
400
t_SC
µs
30
–
90
t_PLH
µs
–
1.0
5.0
t_PHL
µs
–
1.0
5.0
Falling Edge of CSB to Rising Edge of SCLK
• Required Setup Time
t _LEAD
100
–
ns
–
Falling Edge of SCLK to Rising Edge of CSB
• Required Setup Time
SI to Rising Edge of SCLK
• Required Setup Time
t _LAG
50
–
t _{SI (SU)}
16
–
ns
–
ns
–
Rising Edge of SCLK to SI
• Required Hold Time
t _{SI (HOLD)}
20
–
ns
–
SI, CSB, SCLK Signal Rise Time ⁽¹⁷⁾
t _{R (SI)}
–
5.0
–
ns
SI, CSB, SCLK Signal Fall Time ⁽¹⁷⁾
t _{F (SI)}
–
5.0
–
ns
Time from Falling Edge of CSB Low-impedance ⁽¹⁸⁾
t _SO(EN)
–
–
55
ns
Time from Rising Edge off CSB to SO High-impedance ⁽¹⁹⁾
t _SO(DIS)
–
–
55
ns
Time from Falling Edge of SCLK to SO Data Valid ⁽²⁰⁾
t _VALID
–
25
55
ns
Sequential Transfer Rate
• Time required between data transfers
t_STR
µs
–
–
1.0
Notes
16. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
17. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent occurrence of double pulsing.
18. Time required for valid output status data to be available on SO pin.
19. Time required for output states data to be terminated at SO pin.
20. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33813
17