33813 Datasheet, PDF (16/54 Pages) Freescale Semiconductor, Inc – One Cylinder Small Engine Control IC

4.3 Dynamic Electrical Characteristics
Table 5. Dynamic Electrical Characteristics ⁽¹⁵⁾
Characteristics noted under conditions of 6.0 V  V_PWR  18 V, -40 C  T_C  125 C, and Calibrated Timers, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V_PWR = 13 V, T_A = 25 C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Required Low State Duration on V_CC for Power On Reset
• V_CC  0.2 V
t _RESET
1.0
–
s
–
Power on RESET pulse width
t_(POR)
100
-
-
s
WATCHDOG TIMER
Maximum Time Value Watchdog can be loaded with (default time)
Minimum Time Value Watchdog can be loaded with
Reset Pulse Width when Watchdog times out
VRS CONDITIONING INPUT
WDMAX
–
–
WD_MIN
1.0
–
WD_RESET
100
–
10
sec.
–
ms
–
s
Output Blanking Time Programming Range 
(% of previous out pulse 0 to 15/32 in 1/32 steps, 15/32 = 46.9%)
Output Deglitch Filter Time (1/128 of the previous output pulse)
Delay from CSB to Change in VRS Comparator Threshold - GBD
Delay from CSB to Change in VRS Output Blank Time - GBD
ISO9141 TRANSCEIVER
OUTPUT_BLANK
0
OUTPUT_DEGLI
–
TCH
DELAY_THRESH
–
DELAY_OBT
–
–
50
%
1.0
–
%
–
10
s
–
10
s
Typical ISO9141 Data Rate
Turn OFF Delay MTX Input to ISO Output
Turn ON/OFF Delay ISO Input to MRX Output
Rise and Fall Time MRX Output (measured from 10% to 90%)
Maximum Rise and Fall Time MTX Input (measured from 10% to 90%)
ISO_BR
–
t_TXDF
–
t_RXDF, t_RXDR
–
t_RXR, t_RXF
–
t_TXR, t_TXF
–
10
–
kbps
–
2.0
s
–
1.0
s
–
1.0
s
–
1.0
s
ALL LOW SIDE DRIVERS
Output ON Current Limit Fault Filter Timer
t_SC1
30
60
90
µs
Output Retry Timer
t_REF
7.0
10
13
ms
Inrush Current Delay Timer
t_INRUSH
7.0
10
13
ms
Output OFF Open Circuit Fault Filter Timer
t_(OFF)OC
100
–
400
µs
Output Slew Rate
Z_LOAD = 14 and10 mHV_LOAD = 14 V
t _SR(RISE)
V/s
1.0
5.0
10
Output Slew Rate INJOUT1, ROUT1, ROUT2 and LAMPOUT
• Z_LOAD = 14 and10 mH, V_LOAD = 14 V
t _SR(FALL)
V/s
1.0
5.0
10
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
t_PHL
• Input at 50% V_DD to Output voltage 90% of V_LOAD (INJ1, ROUT1, ROUT2,
LAMP)
µs
–
1.0
5.0
Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50% V_DD to Output voltage 90% of V_LOAD (TACHOMETER)
t_PHL
µs
–
1.0
6.0
Notes
15. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33813
16