MC81F4104 Datasheet, PDF (93/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
Release the STOP mode
The source for exit from STOP mode is hardware reset, external interrupt, Timer(EC2,3). Reset re-
defines all the Control registers but does not change the on-chip RAM. External interrupts allow both
on-chip RAM and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution
starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.
(refer to Figure 21-3) When exit from Stop mode by external interrupt, enough oscillation stabilization
time is required to normal operation. Figure 21-4 shows the timing diagram. When released from the
Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The
count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set
its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that
oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 21-5.
Figure 21-3 STOP Releasing Flow by Interrupts
October 19, 2009 Ver.1.35
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