MC81F4104 Datasheet, PDF (57/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
11. INTERRUTP CONTROLLER
External Interrupt 0
External Interrupt 1
External Interrupt 2
Timer2 matchInterrupt
Timer2 overflow Interrupt
Timer3 matchInterrupt
Timer3 overflow Interrupt
Watchdog Timer Interrupt
Basic Timer Interrupt
Interrupt
Request
EXT0IR
EXT1IR
EXT2IR
T2MIR
T2OVIR
T3MIR
T3OVIR
WDTIR
BTIR
Interrupt
Enable
EXT0IE
EXT1IE
EXT2IE
T2MIE
T2OVIE
T3MIE
T3OVIE
WDTIE
BTIE
Release STOP/SLEEP
To CPU
I-flag
Interrupt
Master
Enable
Flag
Interrupt
Vector
Address
Generator
Figure 11-1 Block Diagram of Interrupt
The MC81F4104 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request
flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). And 9 interrupt sources
are provided.
The interrupt vector addresses are shown in „11.5 Interrupt Vector & Priority Table‟ on page 63.
Interrupt enable registers are shown in next paragraph. These registers are composed of interrupt
enable flags of each interrupt source and these flags determine whether an interrupt will be accepted
or not. When the enable flag is “0”, a corresponding interrupt source is disabled.
Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
October 19, 2009 Ver.1.35
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