MC81F4104 Datasheet, PDF (79/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
Function Description
Interval Timer Mode
A match signal is generated and T3O pins are toggled when the T3CR register value equals the
T3DR register value. The match signal generates a timer match interrupt and clears the T3CR
register.
Capture Mode
In capture mode, you have to set EXT2 interrupt. When the EXT2 interrupt is occurred, the T3CR
register value is loaded into the T3DR register and the T3CR register is cleared.
And the timer 3 overflow interrupt is generated whenever the T3CR value is overflowed.
So, If you count how many overflow is occurred and read the T3DR value in EXT2 interrupt routine, it
is possible to measure the time between two EXT2 interrupts. Or it is possible to measure the time
from the T3 initial time to the EXT2 interrupt occurred time.
The time = ( 256 * tCLK ) * overflow_count + (tCLK * T3DR)
Note
„tCLK‟ is the period time of the timer-counter‟s clock source
You must set the T3DR value before set the T3SCR register. Because T3DR value is
fetched when the count is started(the T3CC bit is set) or match/overflow event is occurred.
October 19, 2009 Ver.1.35
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