MC81F4104 Datasheet, PDF (80/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
18. High Speed PWM
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EC2
Counter stop
M
U
X
T2CS
2-bit
8-Bit Up Counter
(Read - only)
R
T2CR
Clear
2-bit 8-Bit Comparator
Match
2-bit Timer 2 Buffer Register
PPH,
PPL
2-bit Timer 2 Data Register
T2DR
2-bit 8-Bit Comparator
2-bit PWM 2 Buffer Register
P2DH,
P2DL
2-bit PWM 2 Data Register
NOTE:
1. When you cleared the POL2 and counter stop, PWM2O is high status.
2. When you set the POL2 and counter stop, PWM2O is low status.
T2CC
Match signal
T2MIE
Timer 2 match INT enable
T2MIR
Timer 2 match INT request
T2 Match
Interrupt
SQ
R
POL2
M
U
PWM2O
X
Counter stop
T2CC
Overflow signal
Match signal
Figure 18-1 High Speed PWM Block Diagram
The MC81F4104 has one high speed PWM (Pulse Width Modulation) function which shared with
Timer2.
In PWM mode, the R04/PWM2O pin operates as a 10-bit resolution PWM output port. For this mode,
the R04 of R0CONM should be set to alternative function mode.
The period of the PWM output is determined by the T2DR (T2 data Register) and PWMPDR[1:0]
(PWM Period Duty Register) and the duty of the PWM output is determined by the PWM2DR(PWM 2
Data Register) and PWMPDR[3:2] (PWM Period Duty Register).
User can use PWM data by writing the lower 8-bit period value to the T2DR and the higher 2-bit
period value to the PWMPDR[1:0]. And the duty value can be used with the PWM2DR and the
PWMPDR[3:2] in the same way.
The bit POL2 of PWMSCR decides the polarity of duty cycle. The duty value can be changed when
the PWM outputs. However the changed duty value is output after the current period is over. And it
can be maintained the duty value at present output when changed only period value shown as
Example of PWM2. As it were, the absolute duty time is not changed in varying frequency.
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October 19, 2009 Ver.1.35