MC81F4104 Datasheet, PDF (90/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
21. POWER DOWN OPERATION
In the power-down modes, power consumption is reduced considerably. For applications where power
consumption is a critical factor, device provides two kinds of power saving functions, STOP mode and
SLEEP mode. Table 21-1 on page 95 shows the status of each Power Saving Mode. SLEEP mode is
entered by the SSCR register to “0Fh”. and STOP mode is entered by STOP instruction after the
SSCR register to “5Ah”.
21.1 Sleep Mode
In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are
operated normally but CPU stops. Movement of all peripherals is shown in Table 21-1 on page 95.
SLEEP mode is entered by setting the SSCR register to “0Fh”. It is released by Reset or interrupt. To
be released by interrupt, interrupt should be enabled before SLEEP mode.
SSCR
STOP AND SLEEP CONTROL REGISTER
00F5H
7
6
5
4
3
2
1
0
SSCR
One byte register
Reset value: 00H
W
W
W
W
W
W
W
W
It is used to set the stop or sleep mode.
5Ah : STOP
0Fh : SLEEP
Note :
To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.
At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when
released.
To get into SLEEP mode, SSCR must be set to 0FH.
Release the SLEEP mode
The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control
registers but does not change the on-chip RAM.(Be careful, If the code is compiled with RAM clear
option, RAM is cleared after reset by ram clear routine. It is possible to disable the RAM clear option
by option menu). Interrupts allow both on-chip RAM and Control registers to retain their values. If I-
flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting
with the instruction following the SLEEP instruction. It will not vector to interrupt service routine. (refer
to Figure 21-3)
When exit from SLEEP mode by reset, enough oscillation stabilization time is required to normal
operation. Figure 21-2 shows the timing diagram. When released from the SLEEP mode, the Basic
interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to
start normal operation.
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October 19, 2009 Ver.1.35