MC81F4104 Datasheet, PDF (75/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
Function Description
Interval Timer Mode
A match signal is generated and T2O pins are toggled when the T2CR register value equals the
T2DR register value. The match signal generates a timer match interrupt and clears the T2CR
register.
Capture Mode
In capture mode, you have to set EXT0 interrupt. When the EXT0 interrupt is occurred, the T2CR
register value is loaded into the T2DR register and the T2CR register is cleared.
And the timer 2 overflow interrupt is generated whenever the T2CR value is overflowed.
So, If you count how many overflow is occurred and read the T2DR value in EXT0 interrupt routine, it
is possible to measure the time between two EXT0 interrupts. Or it is possible to measure the time
from the T2 initial time to the EXT0 interrupt occurred time.
The time = ( 256 * tCLK ) * overflow_count + (tCLK * T2DR)
Note
„tCLK‟ is the period time of the timer-counter‟s clock source
You must set the T2DR value before set the T2SCR register. Because T2DR value is
fetched when the count is started(the T2CC bit is set) or match/overflow event is occurred.
October 19, 2009 Ver.1.35
75