MC81F4104 Datasheet, PDF (24/118 Pages) Finechips – ABOV SEMICONDUCTOR

MC81F4104
7.7 Data Retention Voltage in Stop Mode
(T_A = - 40 ^C to + 85^C, V_DD = 2.2 V to 5.5 V)
Parameter
Symbol
Conditions
Min Typ Max
Data retention supply _VDDDR
–
voltage
2.2
–
5.5
Data retention supply
current
IDDDR
VDDDR = 2.2V
(TA = 25 C), Stop mode
–
–
1
Units
V
uA
V DD
INT Request
Execution of
STOP Instruction
Stop Mode
Data Retention
VDDDR
IDLE Mode
(Watchdog Timer Active)
Normal
Operating Mode
0.8VDD
t WAIT
VDD
RESETB
NOTE: tWAIT is the same as 256 X 1/BT Clock
Figure 7-3 Stop Mode Release Timing When Initiated by an Interrupt
RESET
Occurs
Stop Mode
Data Retention
Oscillation
Stabillization Time
Normal
Operating Mode
Execution of
STOP Instruction
V DDDR
0.2 VDD
0.8 VDD
TWAIT
NOTE: tWAIT is the same as 256 X 1024 X 1/fxx (65.5mS @4MHz)
Figure 7-4 Stop Mode Release Timing When Initiated by RESETB
7.8 LVR (Low
Electrical Characteristics
(T_A = - 40 ^C to + 85^C, V_DD = 2.2 V to 5.5 V)
24
Voltage Reset)
October 19, 2009 Ver.1.35