FAN5240 Datasheet, PDF (9/19 Pages) Fairchild Semiconductor – Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM

PRODUCT SPECIFICATION
FAN5240
Operation Mode Control
The mode-control circuit changes the converter’s mode of
operation from PWM to Hysteretic and visa versa, based
on the voltage polarity of the SW node when the lower
MOSFET is conducting and just before the upper MOSFET
turns on. For continuous inductor current, the SW node is
negative when the lower MOSFET is conducting and the
converters operate in fixed-frequency PWM mode as shown
in Figure 4. This mode of operation achieves high efficiency
at nominal load. When the load current decreases to the point
where the inductor current flows through the lower MOSFET
in the ‘reverse’ direction, the SW node becomes positive,
and the mode is changed to hysteretic, which achieves higher
efficiency at low currents by decreasing the effective switch-
ing frequency.
To prevent accidental mode change or “mode chatter” the
transition from PWM to Hysteretic mode occurs when the
SW node is positive for eight consecutive clock cycles
(see Figure 4). The polarity of the SW node is sampled at the
end of the lower MOSFET's conduction time. At the transi-
tion between PWM and hysteretic mode both the upper and
lower MOSFETs are turned off. The phase node will ‘ring’
based on the output inductor and the parasitic capacitance on
the phase node and settle out at the value of the output volt-
age.
The boundary value of inductor current, where current
becomes discontinuous, can be estimated by the following
expression.
I_LOAD(DIS) = ⁽---^V---₂-^I--^N_F----_S-–---_W-^V----_L^O---_O-^U---_U-^T---_T⁾---^VV----^OI--_N--^U----^T-
(4)
Hysteretic Mode
Conversely, the transition from Hysteretic mode to PWM
mode occurs when the SW node is negative for 8 consecutive
cycles.
A sudden increase in the output current will also cause a
change from hysteretic to PWM mode. This load increase
causes an instantaneous decrease in the output voltage due to
the voltage drop on the output capacitor ESR. If the load
causes the output voltage (as presented at VSNS) to drop
below the hysteretic regulation level (20mV below VREF),
the mode is changed to PWM on the next clock cycle. This
insures the full power required by the increase in output
current.
In hysteretic mode, the PWM comparator and the error
amplifier that provide control in PWM mode are inhibited
and the hysteretic comparator is activated. In hysteretic
mode the low side MOSFET is operated as a synchronous
rectifier, where the voltage across VDS(ON) is monitored,
and its gate switched off when VDS(ON) goes positive
(current flowing back from the load) blocking reverse
conduction
The hysteretic comparator initiates a PFM signal to turn on
HDRV when the output voltage (at VSNS) falls below the
lower threshold (10mV below VREF) and terminates the
PFM signal when VSNS rises over the higher threshold
(5mV above VREF).
The switching frequency is primarily a function of:
1. Spread between the two hysteretic thresholds
2. ILOAD
3. Output Inductor and Capacitor ESR
A transition back to PWM (Continuous Conduction Mode or
CCM) mode occurs when the inductor current rises suffi-
ciently to stay positive for 8 consecutive cycles. This occurs
when:
I_LOAD(CCM) = ^∆-----^V----^H---₂-^Y---^S--_E-^T---_S-^E---_R^R----^E---^S----^I--^S-
(5)
where ∆VHYSTERESIS = 15mV and ESR is the equivalent
series resistance of COUT.
Because of the different control mechanisms, the value of the
load current where transition into CCM operation takes place
is typically higher compared to the load level at which transi-
tion into hysteretic mode occurs.
V_CORE
I_L
0
V_CORE
I_{L 0}
REV. 1.1.7 8/29/02
PWM Mode
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Hysteretic Mode
Hysteretic Mode
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4
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Figure 4. Transitioning between PWM and Hysteretic Mode
PWM Mode
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