FAN5240 Datasheet, PDF (3/19 Pages) Fairchild Semiconductor – Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM

PRODUCT SPECIFICATION
Pin Configuration
LDRV2
PGND2
BOOT2
HDRV2
SW2
ISNS2
VID4
VID3
VID2
VID1
VID0
FPWM
ILIM
EN
1
28
2
27
3
26
4
25
5
24
6
23
7
22
FAN5240
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
LDRV1
PGND1
BOOT1
HDRV1
SW1
ISNS1
VIN
SS
PGOOD
VCORE+
VCORED
DELAY
AGND
QSOP-28 or TSSOP-28
θ_JA = 90°C/W
FAN5240
Pin Definitions
Pin
Pin
Number Name
Pin Function Description
1
27
2
26
3
25
4
24
5
23
6
22
7 - 11
12
13
14
15
16
18
17
19
LDRV2 Low-Side Drive. The low-side (lower) MOSFET driver output.
LDRV1
PGND2 Power Ground. The return for the low-side MOSFET driver.
PGND1
BOOT2 BOOT. The positive supply for the upper MOSFET driver. Connect as shown in Figure 1.
BOOT1
HDRV2 High-Side Drive. The high-side (upper) MOSFET driver output.
HDRV1
SW2 Switching node. The return for the high-side MOSFET driver.
SW1
ISNS2 Current Sense input. Monitors the voltage drop across the lower MOSFET or external
ISNS1 sense resistor for current feedback.
VID4 - Voltage Identification Code. Input to VID DAC. Sets the output voltage according to the
VID0 codes set as defined in Table 2. These inputs have 1µA internal pull-up.
FPWM Forced PWM mode. When logic high, inhibits the chip from entering hysteretic operating
mode. If tied low, hysteretic mode will be allowed.
ILIM Current Limit. A resistor from this pin to GND sets the current limit.
EN ENABLE. This pin enables IC operation when either left open, or pulled up to VCC.
Toggling EN will also reset the chip after a latched fault condition.
AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
DELAY Power Good / Over-Current Delay. A capacitor to GND on this pin delays the PGOOD
from going high as well delaying the over-current shutdown.
VCORE+ VCORE Output Sense. Differential sensing of the output voltage. Used for regulation as
VCORE– well as PGOOD, under-voltage and over-voltage protection and monitoring. A resistor in
series with this VCORE+ sets the output voltage droop.
PGOOD Power Good Flag. An open-drain output that will pull LOW when the core output below
825mV. PGOOD delays its low to high transition for a time determined by CDELAY when
VCORE rises above 875mV.
REV. 1.1.7 8/29/02
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