FAN5240 Datasheet, PDF (8/19 Pages) Fairchild Semiconductor – Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM

FAN5240
PRODUCT SPECIFICATION
Initialization, Soft Start and PGOOD
Assuming EN is high, FAN5240 is initialized when power is
applied on VCC. Should VCC drop below the UVLO thresh-
old, an internal Power-On Reset function disables the chip.
The IC attempts to regulate the VCORE output according to
the voltage that appears on the SS pin (VSS). During start-up
of the converter, this voltage is initially 0, and rises linearly
to 90% of the VID programmed voltage via the current sup-
plied to CSS by the 25µA internal current source. The time it
takes to reach this threshold is:
T_90% = ⁰----^.--⁹----^×-----^V----^V-₂---^I₅--^D----^×-----^C-----^S---^S--
(1)
where T90% is in seconds if CSS is in µF.
At that point, the current source changes to 500µA, which
establishes the slew rate of voltage changes at the output in
response to changes in VID.
This dual slope approach helps to provide safe rise of volt-
ages and currents in the converters during initial start-up and
at the same time sets a controlled speed of the core voltage
change when the processor commands to do so.
1.5V
1.35V
SS
EN
PGOOD
TDLY
Figure 3. Soft-Start function
CSS typically is chosen based on the slew rate desired in
response to a VID change. For example, if the spec requires a
500mV step to occur in 100µS:
C_SS
=
∆^-----V^-I--S-_D^--S--_A^---_C^{-- ∆ t}
=


5^-5---0^-0--0^-0---m^-µ---A-V^{---}
100µS
=
0.1µF
(2)
Assuming VID is set to 1.5V, with this value of CSS , the
time for the output voltage to rise to 0.9 of VVID is found
using equation 1:
T_90% = ¹----^.--³---⁵----_2V---₅--^×-----⁰---^.--¹-- = 5.4mS
The transition from 90% VID to 100% VID occupies 0.5%
of the total soft-start time, so TSS is essentially T90%.
The PGOOD delay (TDLY, Figure 3) can be programmed
with a capacitor to GND on pin 16 (CDELAY):
C_DELAY(in nF) = 1.8 × TDLY(in mS)
(3)
For 12mS of TDLY, CDELAY = 22nF.
CDELAY is typically chosen to provide 1mS of "blanking"
for the over-current shut-down (see Over-Current Sensing,
on page 12).
The following conditions set the PGOOD pin low:
1. Under-voltage - VCORE is below a fixed voltage.
2. Chip shut-down due to over-temperature or over-current
as defined below.
Converter Operation (see Figure 2)
At nominal current the converter operates in fixed frequency
PWM mode. The output voltage is compared with a refer-
ence voltage set by the DAC, which appears on the SS pin.
The derived error signal is amplified by an internally com-
pensated error amplifier and applied to the inverting input
of the PWM comparator. To provide output voltage droop for
enhanced dynamic load regulation, a signal proportional to
the output current is added to the voltage feedback signal
at the + input of A1. Since the processor specifies a +100mV/
-50mV tolerance on VCORE, a fixed positive offset of 30
mV is created with a 30µA current source and external 1K
resistor. Phase load balancing is accomplished by adding
a signal proportional to the difference of the two phase
currents before the error amplifier (at nodes A and B). This
feedback scheme in conjunction with a PWM ramp propor-
tional to the input voltage allows for fast and stable loop
response over a wide range of input voltage and output
current variations. For the sake of efficiency and maximum
simplicity, the current sense signal is derived from the volt-
age drop across the lower MOSFET during its conduction
time. This current sense signal is used to set droop levels as
well as for phase balancing and current limiting.
The PWM controller has a built-in duty cycle clamp in the
path from the error amplifier to the PWM comparator.
During a severe load step, the output signal from the error
amp can go to its rail, pushing the duty cycle to almost 100%
for a significant amount of time. This could cause a severe
rise in the inductor current, especially at high battery volt-
age, and lead to a long recovery time or even failure of the
converter. To prevent this, the output of the error amplifier is
clamped to a fixed value after two clock cycles if a large
output voltage excursion is detected. Sensitivity of this
circuit is set in such a way as not to affect the PWM control
during transients normally expected from the load.
8
REV. 1.1.7 8/29/02