FAN5240 Datasheet, PDF (13/19 Pages) Fairchild Semiconductor – Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM

PRODUCT SPECIFICATION
FAN5240
Since the tolerance on the current limit is largely dependent
on the ratio of the external resistors it is fairly accurate if the
voltage drop on the Switching Node side of RSENSE is an
accurate representation of the load current. When using the
MOSFET as the sensing element, the variation of RDS(ON)
causes proportional variation in the ISNS. This value not
only varies from device to device, but also has a typical
junction temperature coefficient of about 0.4% / °C (consult
the MOSFET datasheet for actual values), so the actual
current limit set point will decrease propotional to increasing
MOSFET die temperature. The same discussion applies to
the VDROOP calculation.
Q2
LDRV
21 ^{ISNS RSENSE}
22 ^PGND
Figure 11. Improving current sensing accuracy
More accurate sensing can be achieved by using a resistor
(R1) instead of the RDS(ON) of the FET as shown in Figure
11. This approach causes higher losses, but yields greater
accuracy in both VDROOP and ILIMIT. R1 is a low value
(e.g. 10mΩ) resistor.
The current limit (ILIMIT) set point chosen needs to accom-
modate ripple current, slew current, and variability in the
MOSFET's RDS(ON).
I_LIMIT > I_LOAD + C_OUT^d--_d--^V-_t--
(12a)
Slew current ( C_OUT^d--_d--^V-_t-- ) is the current required for the
output voltage to slew upwards during VID code changes,
since the circuit will limit the regulator’s output current by
pulse skipping when ILIMIT is reached. The ^d--_d--^V-_t-- term we
used earlier in the discussion (set up by the CSS) was
500mV/100µS or 5V/mS. Assuming COUT of 4000µF, the
current required to slew COUT at this rate is:
C_OUT^d--_d--^V-_t-- = 4mF • 5V/mS = 20A
(12b)
which is contributed roughly equally from each phase,
therefore, 1/2 of the slew current comes from a single phase.
The over-current comparator is sampled just after LDRV is
turned on, when the current is near its peak in the cycle.
Assuming 20% inductor ripple current, we can then add 1/2
of the ripple current, or 10%. An additional factor of 1.2
accounts for the inaccuracy in the initial (room temperature)
RDS(ON) of the MOSFETs with an additional factor of 1.4 to
accommodate the rise of the MOSFET RDS(ON) when oper-
ating with TJ @ 125°C. With a maximum load current of
12.5A/phase, the target for ILIMIT (per phase) would be:
I_LIMIT
>
1.1
•
1.2
•
1.4
•


12.5A
+
2_----02_----A_{--}
≈
42A
(12c)
so using equation 11, with RDS(ON) = 3mΩ for the 2 parallel
FDS6688 MOSFETs, RILIM ≈ 56K:
Over-Voltage Protection
Should the output voltage exceed 2.35V due to an upper
MOSFET failure, or for other reasons, the overvoltage
protection comparator will force the LDRV high. This action
actively pulls down the output voltage and, in the event of
the upper MOSFET failure, will eventually blow the battery
fuse. As soon as the output voltage drops below the thresh-
old, the OVP comparator is disengaged.
This OVP scheme provides a ‘soft’ crowbar function which
helps to tackle severe load transients and does not invert the
output voltage when activated — a common problem for
OVP schemes with a latch.
Over-Temperature Protection
The chip incorporates an over temperature protection circuit
that shuts the chip down when a die temperature of 150°C is
reached. Normal operation is restored at die temperature
below 125°C with internal Power On Reset asserted, result-
ing in a full soft-start cycle.
REV. 1.1.7 8/29/02
13