FAN5240 Datasheet, PDF (12/19 Pages) Fairchild Semiconductor – Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM

FAN5240
C2
R2 C1
R1
V_IN
–
REF ⁺
EAOut
PRODUCT SPECIFICATION
Over-Current sensing (see Figure 10)
When the circuit's current limit signal (“ILIM det” as shown
in Figure 6) goes high, a pulse-skipping circuit is activated
and a 16-clock cycle counter is started. HDRV will be inhib-
ited as long as the sensed current is higher than the ILIM
value. This limits the current supplied by the DC input.
Error _Amp ^Converter
Modulator
18
14
0
F_P0
F_Z
F_P
Figure 9. Compensation
F_Z = -₂---_π----_R--¹--₂---_C-----₁- = 6 kHz
(9a)
F_P = -₂---_π----_R--¹--₂---_C-----₂- = 600 kHz
(9b)
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends on
how wide the region of flat gain is and has a maximum value
of 90 degrees. To further simplify the converter compensa-
tion, the modulator gain is kept independent of the input
voltage variation by providing feed-forward of VIN to the
oscillator ramp.
The zero frequency, the amplifier high frequency gain and
the modulator gain are chosen to satisfy most typical appli-
cations. The crossover frequency will appear at the point
where the modulator attenuation equals the amplifier high
frequency gain. The only task that the system designer has to
complete is to specify the output filter capacitors to position
the load main pole somewhere within one decade lower than
the amplifier zero frequency. With this type of compensation
plenty of phase margin is easily achieved due to zero-pole
pair phase ‘boost’.
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’. Fortunately, there is an oppo-
site trend in mobile applications to keep the output capacitor
as small as possible.
Protection
The converter output is monitored and protected against
short circuit (over-current), and over-voltage conditions.
12
Clock
ILIM det. 1
ILIM det. 2
16 Clock
Counter and
Logic
Shut-down
RESET
Q TIMER
START
DELAY
Figure 10. Over-current shut-down delay logic
If ILIM det goes high during counts 9-16 of the counter, the
overcurrent delay timer is started and the 16-clock counter
starts again. This timer delays the shut-down of the chip and
its time is a function of the value of CDELAY.
T_HOLDOFF(in mS) = -^C----^D----^E---^L---^A--₁--^Y-₉--⁽---ⁱ-ⁿ-----ⁿ---^F-----⁾
(10)
Over-current must detected at least once during the first 8
clock cycles and once during the 2^nd 8 clock cycles of the
16-cycle counter for the timer to continue timing. If the over-
current condition does not occur at least once per 8 clock
counts during any clock counter cycle while the timer is
high, the timer and the over-current detection circuit are
reset, preventing shutdown. The clock counter coutinues to
count and look for ILIM det pulses in this manner until
either:
1. the IC is shut-down because the timer timed out:
If the timer pulse is allowed to finish by timing out, the
IC is shut-down and can only be restarted by removing
power or toggling the EN pin.
2. ILIM det does not go high at least once per 8 clock
counts. In this case, the timer and over-current shutdown
logic are reset, and a chip shut-down is averted.
PGOOD will go LOW if the IC shuts down from over-
current.
Setting the Current Limit
ISNS is compared to the current established when a 0.9 V
internal reference drives the ILIM pin. The threshold is
determined at the point when the
I_---S_---8-N_-----S_{-- > -R-}0_---._I--9_L---IV_{-M--- . Since ISNS = -}^I_-L_---O_----A_---R-D_---S--^•_--E--^R_-N----DS_---S_-E---(_--O_----N_---)
therefore,
R_ILIM = _I--⁰_L---^._I--⁹_M---^V-_I--_T- × -⁸----^•--_R---⁽--_D^R---_S--^S--₍-^E-_O---^N-_N--^S-₎---^E----⁾
(11)
REV. 1.1.7 8/29/02