FAN5231 Datasheet, PDF (9/17 Pages) Fairchild Semiconductor – Precision Dual PWM Controller And Linear Regulator for Notebook CPUs

FAN5231
not the same because the CPU current is significantly lower
as it is illustrated by the following equaton.
I_CPU = K_CPU • V_CPUi • F_CPUi • K_F;
Where, K_CPU — is a processor constant; V_CPUi — is proces-
sor operating voltage; F_CPUi — is processor clock frequency;
K_F — is a coefficient that varies from 0 to 1 and indicates
how heavily processor is engaged by the software; i — is a
denominator associated with the processor mode of opera-
tion (performance or battery optimized).
V_CPU =1.6V
1
I_CPU =0.3A>>18A
2
Ch1 50mV
Ch2 5.0A
M50µs
Figure 4.
This leads to deterioration of the droop benefits in the
battery-optimized mode where they are mostly appreciable,
Fig. 3.
V_CPU =1.35V
1
I_CPU = 0.3A>>1.3 5A
2
V_CPU =1.00V
1
I _CPU =0.3A>>12.0A
2
Ch1 50mV
Ch2 5.0A
M50µs
Figure 6.
To accommodate the droop the output voltage of core
converter is raised 2% at no load conditions. The resistor
connected to ISEN1 pin programs the amount of droop.
R_CS = ^I---^M----^A---^X---7--^â‹-5--^R-_µ---^D-_A---^S--⁽--^O----^N----⁾
This resistor sets the gain in the current feedback loop. The
droop is scaled to 5.5% of the VID code when current into
ISEN1 pin equals 75µA.
The output voltage waveforms with droop subjected to load
step are shown on Fig. 4–Fig. 6 .
Feedback Loop Compensation
Due to implemented average current mode control, the
modulator has a single pole response with -1 slope at
frequency determined by load
F_PO = -2---_π-----_â‹---R-1---₀----_â‹---_C----₀- _’
where Ro – is load resistance, Co – is load capacitance. For
this type of modulator Type 2 compensation circuit is usually
sufficient. To reduce number of external components and
remove the burden at determining compensation components
from a system designer, both PWM controllers have
internally compensated error amplifiers.
Ch1 50mV
Ch2 5.0A
M5 0µs
Figure 5.
The FAN5231 incorporates a new proprietary droop
technique specially designed for the SpeedStep-enabled
converters and provides mode-compensated, relatively equal
droop in both, the performance and the battery-optimized
modes. The droop is set as a fraction of the VID programmed
voltage and the gain in the current loop is different for each
VID combination, those providing the droop, which is
compensated for the voltage and the frequency changes
associated with the different CPU modes of operation.
Figure 7 shows Type 2 amplifier and its response along with
responses of current mode modulator and the converter. The
Type 2 amplifier, in addition to the pole at origin, has a zero-
pole pair that causes a flat gain region at frequencies in
between the zero and the pole.
F_Z = -2---_π-----_â‹---R-1---₂----_â‹---_C----₁-= 6kHz;
F_P = _2----π-----_â‹---R-1---₂----_â‹---_C----₁-= 600kHz;
REV. 1.1.1 8/15/01
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