FAN5231 Datasheet, PDF (2/17 Pages) Fairchild Semiconductor – Precision Dual PWM Controller And Linear Regulator for Notebook CPUs

FAN5231
Description
The FAN5231 is a highly integrated power controller, which
provides a complete power management solution for mobile
CPUs. The IC integrates two PWM controllers and a linear
regulator as well as monitoring and protection circuitry into
a single 28-lead plastic SSOP package. The two PWM
controllers regulate the microprocessor core and I/O voltages
with synchronous-rectified buck converters, while the linear
regulator powers the CPU clock.
The FAN5231 includes 5-bit digital-to-analog converter
(DAC) that adjusts the core PWM output voltage from
0.925VDC to 2.0VDC and conforms to the Intel Mobile
VID specification. The DAC setting may be changed during
operation to accommodate Dual-Mode processors. Special
measures are taken to provide such a transition with con-
trolled rate in a specified 100 µs. A precision reference,
remote sensing, and a proprietary architecture with inte-
grated processor mode-compensated "droop" provide excel-
lent static and dynamic core voltage regulation. The second
PWM controller has a fixed 1.5V output voltage and powers
the I/O circuitry. Both PWM controllers have integrated
feedback-loop compensation that dramatically reduces the
number of external components. At nominal loads PWM
controllers operate at fixed frequency 300kHz. At light loads
when the filter inductor current becomes discontinuous,
controllers operate in a hysteretic mode. The out-of-phase
operation of two PWM controllers reduces input current
ripple in both modes of operation. The linear regulator uses
an internal pass device to provide 2.5V for the CPU clock
generator.
The FAN5231 monitors all the output voltages. A single
Power-Good signal is issued when soft start is completed
and all outputs are within ±10% of their respective set points.
A built-in over-voltage protection for the core and I/O out-
puts forces the lower MOSFETs on to prevent output volt-
ages from going above 115% of their settings. Under-voltage
protection latches the chip off when any of the three outputs
drops below 75% of the set value. The PWM controller's
overcurrent circuitry monitors the output current by sensing
the voltage drop across the lower MOSFETs. If precision
overcurrent protection is required, an external current-sense
resistor may be used.
Block Diagram
LI NEAR REGULA TOR
V3I N
VOUT3
-
0.9V
VBATT
EN VCC GND
RAMP 2
CLK
FFBK 1
RAMP 1
CLK 2
CLK1
POWER-ON
RESET (POR)
BOOT2
UGATE2
PHASE2
H GDR2
LG ATE2
PGND2
GATE
CONTROL
VCC
LG DR2
OV P2
HI
FL OGON
SHUTOFF
GATE LOGI C 2
DEADT
PWM /HYST
PWM ON
LO
HYST ON
PWM VCC
LATCH 1
QD
R
Q<
-
HY ST COM P2
-
CLK2
OC COM P2
VSEN2
EA2
-
2.8V ^-
0.9V
MO DE
CONTROL
COMP 2
+
-
LG ATE2
ISEN2
R1=20k
LG ATE2
OC LOGI C2
VCC ^PWM
LATCH 2
DYNA MI C
DUTY CYCLE _∑
CLAMP
-
DQ
R
<Q
-
MO DE
PHASE1
CONTROL
LO GI C 1
FL OGON
HI
SHUTOFF
GATE L OGI C 1
FCCM
DEADT
PWM /HYST
PWM ON
HYST ON
LO
OC COMP1
OC LOGI C1
-
HGDR1
GATE
CONTROL
VCC
LGDR1
OV P1
HY ST COM P1
-
CLK 1
DAC OUT
BOOT1
UGATE1
PHASE1
LG ATE1
PGND1
DYNAM I C
DUTY CYCLE
CLAMP
EA1
-
FFBK 1
MO DE
CONTROL PHASE1
LO GIC 1
PRE AM P _VSEN1
∑
+
-
VRET 1
-
+ ^{FAST FEEDBACK COMP 1}
LG ATE1
LG ATE1
R1= 20k
-
ISEN1
OUTPUT
VOLTAGE
MO NIT OR
OVP1
OVP2 ^FCCM
TTL DAC
REFERENCE
SOFT START
PGOOD
VI D0 VI D2 VI D4 SOFT
VI D1 VI D3
2
REV. 1.1.1 8/15/01