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FAN5231 Datasheet, PDF (8/17 Pages) Fairchild Semiconductor – Precision Dual PWM Controller And Linear Regulator for Notebook CPUs
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FAN5231
The ‘11111’ and ‘0111‘VID codes, as shown in Table 1, shut
the IC down and set PGOOD low.
Table 1.
Pin Name
VID4 VID3 VID2 VID1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Nominal OUT1
Voltage
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
No CPU*
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
No CPU*
Note:
1. 0 = connected to GND or VSS, 1 = open or connected to
3.3V through pull-up resistors.
Core Converter PWM Operation
At the nominal current core converter operates in a fixed
frequency PWM mode. The output voltage is compared with
a reference voltage set by the DAC. The derived error signal
is amplified by an internally compensated error amplifier and
applied to the inverting input of the PWM comparator.
To provide output voltage droop for enhanced dynamic load
regulation, a signal proportional to the output current is
added to the voltage feedback signal. This feedback scheme
in conjunction with a PWM ramp proportional to the input
voltage allows for fast and stable loop response over a wide
range of input voltage and output current variations. For the
sake of efficiency and maximum simplicity, the current sense
signal is derived from the voltage drop across the lower
MOSFET during its conduction time.
Mode-Compensated Droop
An output voltage "droop" or an active voltage positioning is
now widely used in the computer power applications. The
technique is based on raising the converter voltage at light
load in anticipation of the possible load current step. Con-
versely, the output voltage is lowered at high load in antici-
pation of possible load drop. The output voltage varies with
the load like it is a resistor connected in series with the con-
verter’s output. When done as part of the feedback in a
closed loop, the "droop" is not associated with substantial
power losses, though. There is no such resistor in a real cir-
cuit, but rather the feature is emulated by the feedback.
The "droop" allows a reduction in size and cost of the output
capacitors required to handle the transient. Additionally to
that, the CPU power dissipation is also slightly reduced as it
is proportional to the applied voltage squared and even slight
voltage decrease translates in a measurable reduction in
power dissipated.
VCPU
Performance Mode
1.6
Battery-Optimized Mode
1.35
Traditional Droop
Mode-Compensated Droop
0
5
10 ICPU
Figure 3. Mode-Compensated Droop
When powering the dual mode processor, it is desired to
have an adequate "droop" (equal fractions of the pro-
grammed output voltage) in both performance and battery-
optimized modes of operation. The traditional "droop" is
normally tuned to the worse case load, which is associated
with the performance mode. In the battery optimized mode,
the CPU operating voltage and the clock frequency are both
scaled down. Due to the constant gain in the current loop, the
traditional "droop" compensates only for the operating volt-
age change. The degree of the droop achieved in this case is
8
REV. 1.1.1 8/15/01
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