FAN5231 Datasheet, PDF (7/17 Pages) Fairchild Semiconductor – Precision Dual PWM Controller And Linear Regulator for Notebook CPUs

FAN5231
Description
Operation Overview
The FAN5231 three-in-one power mangement integrated
circuit provides complete power solution for modern proces-
sors for notebook and sub-notebook PCs. The IC controls
operation of two synchronous buck converters and one linear
regulator. The output voltage of the core converter can be
adjusted in the range from 0.925V to 2.0 by changing the
DAC code settings (see Table 1). The output voltage of the
I/O converter is fixed to 1.5V. The internal linear regulator
provides fixed 2.5V for the CPU clock generator from the
system +3.3V bus. The output voltage of the core converter
can be changed on-the-fly with programable slew rate, which
makes it especially suitable for the processors that feature
modern power savings techniques as SpeedStep™ or Power-
Now!™ .
Both, core and I/O converters can operate in two modes:
fixed frequency PWM and variable frequency hysteretic
depending on the load level. At loads lower than the critical
where filter inductor current becomes discontinuous, hyster-
etic mode of operation is activated. Switchover from PWM
to hysteretic operation at light loads improves the converters'
efficiency and prolongs battery run time. In hysteretic mode,
comparators are synchronized to the main clock that allows
seamless transition between the operational modes and
reduced channel-to-channel interaction. As the filter inductor
resumes continuous current, the PWM mode of operation is
restored.
In this mode SOFT has both sourcing and sinking capabili-
ties to maintain voltage across the soft-start capacitor con-
forming to the VID code.
This dual slope approach helps to provide safe rise of volt-
ages and currents in the converters during initial start-up and
at the same time sets a controlled speed of the core voltage
change when the processor commands to do so.
Soft-start circuits for the I/O converter is slaved to the core
output soft-start circuit and they complete their ramp-up
when voltage on the SOFT pin reaches 0.9V.
1
2
3
4
(1) Ch1 V_CPU 500mV (2) Ch2 V_IO 500mV
(3) Ch3 V_CLK 1.0V (4) Ch4 V_EN 5.0V
M1.00ms
V_IN = 20V
Figure 2. Initial Startup
The core converter incorporates a proprietary output voltage
droop circuit for optimum handling of the fast load transients
found in modern processors. The droop is compensated for
the processor mode changes, which allows for relatively
equal droop in any operation mode and to specify the droop
as a fraction of the VID set voltage.
Initialization
The FAN5231 initializes upon receipt of input power assum-
ing EN is high or not connected. The Power-On Reset (POR)
function continually monitors the input supply voltage on the
VCC pin and initiates soft-start operation after input supply
voltage exceeds 4.5V. Should this voltage drop lower than
4.0V, POR disables the chip.
Soft-Start
When soft start is initiated, the voltage on the SOFT pin
starts to ramp gradually due to the 25µA current sourced into
the external capacitor.
When SOFT-pin voltage reaches 0.9V, the value of the sourc-
ing current rapidly changes to 500µA charging the soft-start
capacitor to the level determined by the DAC. This completes
the soft start sequence, Fig. 2. As long as the SOFT voltage is
above 0.9V, the maximum value of the internal soft-start cur-
rent is set to 500µA allowing fast rate-of-change in the core
output voltage due to a VID code change.
The value of the soft-start capacitor can be estimated by the
following equation:
Css = _∆-^∆----_VI---^s-_d-^s--_a-^m--_c- ∆t
For the typical conditions when ∆Vdac = 0.25V, ∆t = 100µs
Css = ^{5----0---0---µ}----^A--100µs ≈ 0.2µF
0.25V
With this value of the soft-start capacitor, soft start time will
be equal to:
Tss = ^{0----.-2---µ}--2--^F-5---_µ-^•---_A--0---.-9---^V--- = 7.2ms
OUT1 Voltage Program
This output of PWM1 converter is designated to supply
the microprocessor core voltage. The OUT1 voltage is
programmed to discrete levels between 0.925V_DC and
2.0V_DC as specified in Table 1. The voltage identification
(VID) pins program an internal voltage reference (DAC)
through a TTL-compatible 5-bit digital-to-analog converter.
The level of the DAC voltage also sets the PGOOD, UVP
and OVP thresholds. The VID pins can be left open for a
logic 1 input due to an internal 1µA pull-up to Vcc.
REV. 1.1.1 8/15/01
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