FAN5231 Datasheet, PDF (12/17 Pages) Fairchild Semiconductor – Precision Dual PWM Controller And Linear Regulator for Notebook CPUs

FAN5231
voltage. To eliminate this, the time delay circuit (8:1 counter
which counts the clock cycles) is activated when the overcur-
rent condition is detected for the first time. If after the delay
the overcurrent condition persists, the converter shuts down.
If not - normal operation restores.
temperatures below 125°C trough the full soft-start cycle by
either cycling EN or VCC pin.
The overcurrent protection circuit trips when the peak value
of the lower MOSFET current is higher than the one
obtained from the following equation.
I_OC
=
I_---t-h----•_{-----R----C---S-}
R_DSON
where: R_CS — is a resistor from ISEN pin to PHASE pin;
I_oc — desired overload current trip level; R_DSON - either
r_DS(ON) of the lower MOSFET, or the value of the optional
current sense resistor; I_th - threshold of the current protection
circuitry (140uA).
1.60V_CORE
1
2
3
4
Ch1 500mV
Ch3 1.0V
Ch2 500mV
Ch4 5.0V
1.50V _IO
2.50V_{CL K}
EN
M1 .0ms
In the linear regulator the maximum current of the integrated
power device is actively limited to 250mA that eventually
creates an under-voltage condition and sets the fault latch.
Overvoltage Protection
During operation, severe load dump or a short of an upper
MOSFET can cause the output voltage to increase signifi-
cantly over normal operation range. When the output
exceeds the over-voltage threshold of 115% of the DAC
voltage (1.7V for PWM2), the over-voltage comparator
forces the lower gate driver high and turns the lower
MOSFET on. This will pull down the output voltage and
eventually blow the battery fuse. As soon as output voltage
drops below the threshold, the OVP comparator is disen-
gaged.
The OVP scheme provides a soft crowbar function and does
not interfere with on-the-fly VID code changes. During
downward changes in the converter output voltage, the
condition when the OVP threshold is set before the new
value of the output voltage is reached is quite expectable.
Also, it does not invert output voltage when activated, a
common problem for OVP schemes with a latch.
Overvoltage protection is not provided for the linear
regulator.
Shutdown
When EN (pin 20) is pulled to the ground, chip is disabled
and enters a low-current state. Both high-side and low-side
gate drivers are turned off. This control scheme produces no
negative output voltage at shutdown, Fig. 12. A rising edge
on EN clears the fault latch.
Thermal Shutdown
The chip incorporates an over temperature protection circuit
that shuts all the outputs down when the die temperature of
150°C is reached. Normal operation restores at the die
Figure 12. Shutdown Waveforms
Application Guidelines
Layout Considerations
Switching type of converters even during normal operation
produce short pulses of current which could cause substan-
tial ringing and be a source of EMI pollution if layout con-
strains are not observed.
There are two sets of critical components in a DC-DC con-
verter. The switching power components processing large
amounts of energy at high rate are a source of a noise, and
low power components responsible for bias and feedback
functions, are mainly recipients of the noise. The situation
with the FAN5231 is even more critical as it provides control
functions for two independent converters. Poor layout design
could lead to cross talk between the converters and result in
degraded performance or even malfunction.
A multi-layer printed circuit board is recommended.
Dedicate one solid layer for a ground plane. Dedicate
another solid layer as a power plane and break this plane into
smaller island at common voltage levels.
Notice all the nodes that are subjected to high dV/dt voltage
swing as PHASE1,2 nodes, for example. All surrounding
circuitry will tend to couple the noise from this nodes trough
stray capacitance. Do not oversize copper traces connected
to these nodes. Do not place traces connected to the feedback
components adjacent to these traces.
Keep the wiring traces from the control IC to the MOSFET
gate and source as short as possible and capable to handle
peak currents up to 2A. Minimize the area within gate-
source path to reduce stray inductance and eliminate para-
sitic ringing at the gate.
12
REV. 1.1.1 8/15/01