FAN5231 Datasheet, PDF (10/17 Pages) Fairchild Semiconductor – Precision Dual PWM Controller And Linear Regulator for Notebook CPUs

FAN5231
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends on
how wide the region of flat gain is and has a maximum value
of 90 degrees. To further simplify the converter
compensation, the modulator gain is kept independent of the
input voltage variation by providing feed-forward of V_IN to
the oscillator ramp.
Converter
EA
GEA=18dB
Modulator
F_PO
C2
R2
C1
R1
Type 2 EA
GEA=14dB
F_Z
F_P
F_C
Figure 7.
The zero frequency, the amplifier high-frequency gain and
the modulator gain are chosen to satisfy most of typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within 10kHz...50kHz range gives some
additional phase ‘boost’. Fortunately, there is an opposite
trend in mobile applications to keep the output capacitor as
small as possible.
Automatic Operation Mode Control
The mode control circuit changes the converter’s mode of
operation depending on the level of the load current. At nom-
inal current converter operates in a fixed frequency PWM
mode. When the load current drops lower than the critical
value, inductor current becomes discontinuous and the oper-
ation mode is changed to hysteretic.
The mode control circuit consists of a flip-flop whose out-
puts provide HYST and NORMAL signals. These signals
inhibit normal PWM operation and activate hysteretic com-
parator and diode emulation mode of the synchronous
MOSFET.
The inputs of the flip-flop are controlled by the outputs of
two delay circuits that constantly monitor output of the phase
node comparator. High level on the comparator output dur-
ing PWM cycle is associated with continuous mode of oper-
10
ation. The low level — corresponds to the discontinuous
mode of operation. When the low level on the comparator
output is detected eight times in a row, the mode control flip-
flop is set and converter is commanded to operate in the
hysteretic mode. If during this pulse counting process the
comparator's output happens to be high, the counter of the
delay circuit will be reset and circuit will continue to monitor
for eight low level pulses in a row from the very beginning,
Fig. 8.
VO UT
t
IIN D
t
PHASE
COMP
1 2 34 5 6 7 8
t
MO DE
OF
OPERATI ON
PWM
Hysteretic
t
Figure 8. PWM to Hysteretic Transistion
VO UT
t
IIN D
1 2 3 45 6 7 8
t
PHASE
COMP
t
MODE
OF
OPERATION
Hysteretic
PWM
t
Figure 9. Hysteretic to PWM Transistion
The circuit which restores normal PWM operation mode
works in the same way and is looking for eight in a row high
level pulses on the comparator's output. If during this count-
ing process the comparator’s output happens to be low, the
counter will be reset and the mode control flip-flop will not
change the state. The operation mode will only be changed
when eight pulses in a row fill the counter, Fig 9. This tech-
nique prevents jitter and chatter of the operation mode con-
trol logic at the load levels close to the critical.
Hysteretic Operation
When the discontinuous inductor current is detected, the
mode control logic changes the way the signals in the chip
are processed by entering the hysteretic mode. The compara-
tor and the error amplifier that provide control in the PWM
mode are inhibited and hysteretic comparators are now acti-
vated. Changes are also made to the gate logic.
The synchronous rectifier MOSFET is now controlled in the
diode emulation mode, hence the controlled conduction in
the second quadrant is prohibited.
REV. 1.1.1 8/15/01