FAN5078 Datasheet, PDF (9/16 Pages) Fairchild Semiconductor – DDR/ACPI Regulator Combo

Circuit Description
Overview
The FAN5078 provides five functions:
1. A general purpose PWM regulator, typically used to
generate VDDQ for DDR Memory.
2. A low-dropout linear VTT regulator capable of sinking
and sourcing 1.5A peak.
3. Control to generate 5V DUAL using an external N-
channel to supply power from 5V MAIN in S0 and an
external P-Channel to provide power from 5V Standby
(5VSB) in S3.
4. Drive to generate 5V USB. This signal drives a P-
Channel MOSFET to connect 5V USB to +5VSB in S3.
5. An internal LDO that regulates 3.3V-ALW in S3 mode
from VCC (5VSB). In S3 or S5, this regulator is capable
of 1.25A peak currents with average currents limited by
the thermal design of the PCB.
At initial power-up, or when transitioning from S5, the PWM
regulator is disabled until 5V MAIN is above its UVLO
threshold.
Table 2. ACPI states
EN
3.3 ALW
STATE (S5#) S3#I S4ST# SBSW SBUSB# S3#O VDDQ VTT LDO
S5
LX X
H
H
L OFF OFF ON
S5 M1
HL L
L
H
L ON ON ON
S3
HL H
L
L
L ON ON ON
S0
HH X
H
H
H ON ON OFF
3.3 ALW
LDO
LDO
LDO
3.3V MAIN
5V Dual
OFF
+5VSB
+5VSB
+5 MAIN
5V USB
OFF
OFF
+5VSB
+5 MAIN
Regulator Sequencing
The VCC pin provides power to all logic and analog control
functions of the regulator, including:
1. Power for the 3.3V regulator
2. LDRV gate driver current
3. HDRV boot diode charging current
4. The regulator analog control and logic.
This pin must be decoupled with a X5R ceramic capacitor
(1μF or larger recommended) as close as possible to the VCC
pin. After VCC is above UVLO, the start-up sequence begins
(see Figure 8).
UVLO on VCC discharges SS and resets the IC.
T0 to T3: After initial power-up, the IC ignores logic inputs for
a period (T3-T0) of approximately:
T3 - T0 ≈ 1.7 • C_SS
(1)
where T3-T0 is in mS if C_SS is in nF. At T2 (about 2/3 of the
way from T1 to T3), the 3.3V-ALW LDO is in regulation. The
3.3V LDO's slew rate is limited by the discharge slope of CSS.
If 3.3V MAIN has come up prior to this time, the 3.3V-ALW
node is already pre-charged through the body diode of Q5
(see Figure 1).
T3 to T4: The IC starts VDDQ only if 5V MAIN is above its
UVLO threshold (5V MAIN OK). Provided 5V MAIN is up
before T3, the IC waits about 100μS before initiating soft-start
on VDDQ to allow CSS time to fully discharge. The IC is in
"SLEEP" or S5 state when EN is low. In S5, only the 3.3V
LDO is on. If the IC is in S5 at T4, CSS is held to 0V.
T4 to T5: After VDDQ is stabilized (when C_SS is at about
~1.3V), an internal VDDQ OK is generated that allows the
VTT LDO to start. To ensure that the VDDQ output is not
subjected to large transient currents, the VTT slew rate is
limited by the slew rate of the SS cap. In addition, the VTT
regulator is current limited. VTT is in regulation once C_SS
reaches about 3.8V.
S0 to S3 or S5 M1: The system signals this transition by
dropping the S3#I signal. When this occurs, S3#O goes low,
and the 3.3V LDO turns on. SBSW pulls low to turn on the P-
Channel 5V DUAL switch. SBUSB# pulls low to turn on Q6
when S4ST# is high.
S3 or S5 M1 to S0: The system signals this transition by
raising the S3#I signal. S0 mode is not entered until 5V MAIN
OK, then the following occurs:
ƒ S3#O releases
ƒ SBSW and SBUSB# both pull high to turn off their
P-Channel switches
ƒ The 3.3V LDO turns off.
In most systems, the ATX power supply is enabled when S3#I
goes from high. At that time, 5V and 3.3V MAIN starts to rise.
When the FAN5078’s 5V MAIN pin is above its UVLO
threshold, Q3 and Q5 turn on. This can cause about a 10%
“dip” in both 5V DUAL and 3.3V ALW when Q3 and Q5 turn
on, since at that point, 5V MAIN and 3.3V MAIN are at 90% of
their regulation value.
© 2006 Fairchild Semiconductor Corporation
9
FAN5078 Rev. 1.0.0 • 05/11/06
www.fairchildsemi.com