FAN5078 Datasheet, PDF (10/16 Pages) Fairchild Semiconductor – DDR/ACPI Regulator Combo

5V DUAL
5V Dual "dip"
4.4V
5V MAIN
S3#O
S3#I
Figure 4. S3 to S0 Transition: 5V DUAL
This dip can also occur in 5V USB and 3.3V-ALW if 5V and
3.3V are not fully charged before the 5V MAIN pin exceeds its
threshold. To eliminate the dip, add delay to the 5V MAIN pin,
as shown below. The 5V MAIN pin on the FAN5078 does not
supply power to the IC; it is only used to monitor the voltage
level of the 5V MAIN supply. The pin does have a pull-down
resistor impedance of about 62K and therefore requires a low
value RDLY resistor (see Figure 5 below).
+5MAIN
FROM
ATX
R_{DLY 5V MAIN 4}
C_DLY
Figure 5. Adding Delay to 5V MAIN
Another method to eliminate the potential for this dip is to
instead connect the ATX power supply’s PWR_OK signal to
the 5V MAIN pin. Some systems cannot tolerate the long
delay for PWR_OK (>100mS) to assert, hence the solution in
Figure 5 may be preferable.
If the PWR_OK signal is used, the voltage at the 5V MAIN pin
must reach the 5V MAIN threshold. Since the internal pull-
down resistance of the 5V MAIN pin is 62K, a low value pull-
up should be used. A lower current solution can also be used
by employing the 12V supply to provide adequate pull-up
capability. The circuit in Figure 6 requires that PWR_OK, 12V,
and +5MAIN from the ATX are all up before allowing the IC to
go to S0.
10K
+12V
5V MAIN ₄
5VS B
PWR_OK
Care should also be taken to ensure that 3.3V-ALW does not
glitch during the transition to S0. As shown in Figure 7, the
3.3V internal regulator turns off as soon as 5V MAIN crosses
its rising threshold, releasing S3#O. While the gate
capacitances of Q5, Q7, and Q3 charge sufficiently to turn Q5
on, the load current on 3.3-ALW is supplied by C12. There is
an initial “ESR step” of I_3.3 x ESR_C12, where I_3.3 is the 3.3-ALW
load current. This is followed by a discharge of C12 whose
slope is proportional to ^I3.3 . To ensure that the drop in 3.3-
C12
ALW during this transition does not cause system problems,
use sufficiently low ESR capacitors and a sufficiently low value
for R4 to ensure that 3.3-ALW remains inside the required
system tolerance.
3.3-ALW ^{I3.3 x ESRC12}
3.3V LDO
ON
OFF
S3#O
(Q5 gate)
4.4V
5V MAIN
S3#I
Figure 7. 3.3V-ALW Transition to S0
S5 to S5 M1 or S3: During S5 to S3 transition, the IC pulls
SBSW (or SBUSB# if enabled by S4ST#) low with a 500nA
current sink to limit inrush in Q4 if 5V MAIN is below its UVLO
threshold. At that time, 5V DUAL and 5V USB are discharged.
The limited gate drives control the inrush current through Q4
or Q6 as they charge their respective load capacitances on 5V
DUAL and 5V USB respectively. Depending on the C_GD of Q4
and Q6, the current available from 5VSB, and the size of C_IN
and C15, C13 and C14 may be omitted.
I_Q4(INRUSH)
=
CIN • 5X10^−7
C13 + C_GD(Q4)
I_Q6(INRUSH)
=
C15 • 5X10^−7
C14 + C_GD(Q6)
(2)
If 5V MAIN is above its UVLO threshold, SBSW (or SBUSB# if
enabled by S4ST#) is pulled down with an impedance of
~150Ω. VDDQ and VTT do not start until 5V MAIN OK is true.
Figure 6. Using PWR_OK to Enable 5V MAIN
© 2006 Fairchild Semiconductor Corporation
10
FAN5078 Rev. 1.0.0 • 05/11/06
www.fairchildsemi.com