FAN5078 Datasheet, PDF (14/16 Pages) Fairchild Semiconductor – DDR/ACPI Regulator Combo

Frequency Loop Compensation
The loop is compensated using a feedback network around
the error amplifier.
C1
C2
COMP
VREF
R1
VDDQ
FB
R4
C3
Figure 12. Compensation Network
Figure 12 shows a complete Type 3 compensation network. A
Type 2 compensation configuration eliminates R4 and C3 and
is shown in Figure 1. Since the FAN5078 architecture employs
summing current mode, Type 2 compensation can be used for
most applications. For critical applications that require wide
loop bandwidth and use very low ESR output capacitors, Type
3 compensation may be required. The PSPICE model and
spreadsheet calculator of AN-6006 can be used to calculate
these component values.
Transient response during a rapid decrease in I_LOAD can be
improved by adding a pull-down resistor (> 5K) from the
COMP pin to GND.
operation can be restored by recycling power or toggling the
EN pin.
Under-Voltage Shutdown
If FB stays below the under-voltage threshold for 2μS, the fault
latch is set. This fault is prevented from setting the fault latch
during PWM soft-start (SS < 1.3V).
Over-Current Sensing
If the circuit’s current limit signal (ILIM det shown in Figure 10)
is high at the beginning of a clock cycle, a pulse-skipping
circuit is activated and HDRV is inhibited. The circuit continues
to pulse skip in this manner for the next 8 clock cycles. If, at
any time from the 9^th to the 16^th clock cycle, the ILIM det is
again reached, the fault latch is set. If ILIM det does not occur
between cycle 9 and 16, normal operation is restored and the
over-current circuit resets itself.
This fault is prevented from setting the fault latch during soft-
start (SS < 1.3V).
PGOOD Signal
PGOOD monitors the status of the PWM output as well as
VTT. PGOOD remains low unless all of the conditions below
are met:
ƒ SS is above 3.5V
ƒ Fault latch is cleared
ƒ FB is between 90% and 110% of VREF
ƒ VTT is in regulation.
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-
voltage conditions.
An internal fault latch is set for any fault intended to shut down
the IC. When the fault latch is set, the IC discharges its output
by driving LDRV high until VDDQ IN < 0.5V. LDRV then goes
low until VDDQ IN > 0.8V. This discharges VDDQ without
causing undershoot (negative output voltage).
To discharge the output capacitors, a 40Ω load resistor is
switched in from VDDQ IN to PGND whenever the IC is in
fault condition or when EN is low. After a latched fault,
Figure 13. Over-Current Protection Waveforms
OVP / HS Fault / FB short to GND detection
A HS Fault is detected when there is more than 0.5V from SW
to PGND 350nS after LDRV reaches 4V (same as the current
sampling time).
OVP fault detection occurs if FB > 115% VREF for 16 clock
cycles.
During soft-start, the output voltage could potentially "run
away" if either the FB pin is shorted to GND or R1 is open.
This fault is detected if the following condition persists for
more than 14μS during soft-start:
ƒ VDDQ IN (PWM output voltage) > 1V
ƒ FB < 100mV
Any of these faults sets the fault latch, even during the SS
time (SS < 1.2V).
© 2006 Fairchild Semiconductor Corporation
14
FAN5078 Rev. 1.0.0 • 05/11/06
www.fairchildsemi.com