FAN5078 Datasheet, PDF (2/16 Pages) Fairchild Semiconductor – DDR/ACPI Regulator Combo

Block Diagrams
+5MAIN
R4
+12V
S3#O
Q7
+5VSB
5V USB
C14
C15
Q6
3.3 MAIN
Q5
C12
SBSW
3
SBUSB#
1
S3#O
16
EN
18
S3#I
17
3.3 ALW
15
PGOOD
13
ACPI
CONTROL
&
LOGIC
+5VSB
C4
C3
SS
21
VCC
14
R5
ILIM
20
PWM
VTT
LDO
+5VSB
Q4
+5MAIN
C13
Q3
S3#O
4 ^{5V MAIN}
2 ^S4ST#
5V DUAL
L2
8 ^BOOT
C5
Q1
9 ^HDRV
10 ^SW
11 ^{ISNS R3}
C2
C_IN
L1 VDDQ
Q2
C_OUT
12 ^LDRV
R2
P1 ^GND
23 ^FB _C9
22 ^COMP
R6
R1
C6
7 ^{VDDQ IN}
R9
24 ^{REF IN}
5 ^{VTT SNS}
C8
R10
6 ^{VTT OUT}
C7
Figure 1. Typical DDR/ACPI System Regulation Schematic
Components are selected for a 15A VDDQ output.
© 2006 Fairchild Semiconductor Corporation
2
FAN5078 Rev. 1.0.0 • 05/11/06
www.fairchildsemi.com