FAN5078 Datasheet, PDF (12/16 Pages) Fairchild Semiconductor – DDR/ACPI Regulator Combo

The time it takes SS to reach 0.9V, and VDDQ to achieve
regulation is:
T_0.9
≈
0.9 X C_SS
45
(4)
where T_0.9 is in mS if C_SS is in nF.
CSS charges another 400mV before the PWM regulator’s
fault latch is enabled. When CSS reaches 1.2V, the VTT
regulator begins its soft-start. After VTT is in regulation,
PGOOD is allowed to go HIGH (open).
Reference Output for ULDO Controllers
The FAN5078’s ILIM pin (pin 20) may be used as a
precision 0.9V reference for external ULDO controllers, as
shown in Figure 9. The ILIM pin is on during all ACPI states.
ILIM
20
R3
C1
R5
5VSB
Q1
U1
R1
VOUT
COUT
Figure 9. Using ILIM as a ULDO Reference
R5 in Figure 1 is the current limit setting resistor and
comprises the only DC current path from the ILIM pin to
GND. The circuit is configured so that the reference for the
ULDO is presented at the positive terminal of U1 and draws
negligible DC current. R3 and C1 filter noise that might be
induced if there is significant PCB trace length. C1 should
be placed as close as possible to the op-amp’s input pin. R3
should be placed as close as possible to pin 20 of the
FAN5078 and should be greater than 10K to isolate the
ILIM pin from noise.
Recommended values for the circuit of Figure 9:
R3
R5
C1
R1, R2
50K
See AN-6006
1nF
Per desired VOUT:
VOUT = 0.9 • ⎜⎛1+ ^R1 ⎟⎞
⎝ ^R2 ⎠
COMP
FB
SS/EN
C_SS
4.41K
Reference and
Soft Start
TO
PWM
COMP
S/H
V to I
ISNS
in +
ISNS
in –
ILIM det.
2.5V
I2 =
ILIM*9.6
0.9V
ILIM
mirror
ISNS ^RSENSE
LDRV
PGND
ILIM ^RILIM
Figure 10. Current Limit / Summing Circuits
© 2006 Fairchild Semiconductor Corporation
12
FAN5078 Rev. 1.0.0 • 05/11/06
www.fairchildsemi.com