FAN5078 Datasheet, PDF (15/16 Pages) Fairchild Semiconductor – DDR/ACPI Regulator Combo

To ensure that FB pin open does not cause a destructive
condition, a 1.3μA current source ensures that the FB pin is
high if open. This causes the regulator to keep the output low
and eventually results in an under-voltage fault shutdown
(after PWM SS completes).
COMP
FB
SS
1.3μA
I_SS
–
+ E/A
+
VREF
ISNS
RAMP
–
+ PWM
+
Figure 14. SS Clamp and FB Open Protection
Over-Temperature Protection
The chip incorporates an over-temperature protection circuit
that shuts the chip down when a die temperature of about
150°C is reached. Normal operation is restored when the die
temperature falls below 125°C with internal Power On Reset
asserted, resulting in a full soft-start cycle. To accomplish this,
the over-temperature comparator discharges the SS pin.
VTT Regulator Section (Figure 3)
The VTT regulator includes an internal resistor divider (50K for
each resistor) from the output of the PWM regulator. If the
REF IN pin is left open, the divider produces a voltage 50% of
VDDQ IN. Using a low impedance external precision voltage
divider produces greater accuracy.
The VTT regulator is enabled when S3#I is HIGH and the
PWM regulator’s internal PGOOD signal is true. The VTT
regulator also includes its own PGOOD signal, which is high
when VTT SNS > 90% of REF IN.
FAN5078 Design Tools
AN-6006 provides a PSPICE model and spreadsheet
calculator for the PWM regulator, simplifying external
component selections, and verifying loop stability.
The spreadsheet calculator can be used to calculate all
external component values for the FAN5078. The spreadsheet
calculates compensation components that can be verified in
the PSPICE model to ensure stability.
The PSPICE model in AN-6006 simulates both loop stability
(Bode Plot) and transient analysis, and can be customized
for a wide variety of applications and external component
configurations.
As an initial step, define:
ƒ Output voltage
ƒ Maximum PWM output load current
ƒ Maximum load transient current and maximum allowable
output drop during load transient
ƒ R_DS(ON) of the low-side MOSFET (Q2)
ƒ Maximum allowable output ripple.
Power MOSFET Selection
For a complete analysis of MOSFET selection and efficiency
calculations, see Application Note AN-6005: Synchronous
Buck MOSFET Loss Calculations with Excel Model.
3.3V and VTT LDO Output Capacitors
For stability, use at least 100μF for 3.3V-ALW bypass
capacitor with a minimum ESR of 20mΩ.
The VTT output is typically bypassed with 820μF with at least
30mΩ ESR.
© 2006 Fairchild Semiconductor Corporation
15
FAN5078 Rev. 1.0.0 • 05/11/06
www.fairchildsemi.com