FAN5068 Datasheet, PDF (8/18 Pages) Fairchild Semiconductor – DDR-1/DDR-2 plus ACPI Regulator Combo

PRODUCT SPECIFICATION
FAN5068
Electrical Specifications (continued)
Recommended operating conditions, component values per Figure 1 unless otherwise noted.
Parameter
Control Functions
S3#I, EN Input Threshold
S3#I EN Input Current
Over-Temperature Shutdown
Over-Temperature Hysteresis
S3#O Output Low R_DS(ON)
S3#O Output High Leakage
SBSW Output Low Resistance
SBSW Sink current (note 1)
SBSW Output High (note 2)
Conditions
V(S3#O) = 12V
5V MAIN OK
5V MAIN < UVLO
Min. Typ. Max. Units
1.0 1.25 1.55 V
–1
1
µA
150
°C
25
°C
170 300 Ω
4
10 µA
125 200 Ω
500
nA
820 1200 Ω
Circuit Description
Overview
The FAN5068 provides 5 functions:
1. A general purpose PWM regulator, typically used to gen-
erate VDDQ for DDR memory.
2. A low-dropout linear VTT regulator capable of sinking
and sourcing 1.5A peak.
3. An adjustable Ultra Low Drop Out (ULDO) controller
which, in conjunction with an external N-Channel power
MOSFET, provides a programmable low voltage output.
The power source for this output is typically the VDDQ
output and is used to provide the 1.2V GTL
processor FSB termination voltage.
4. Control for generating a 5V DUAL voltage using an
external N-channel to supply power from 5V MAIN in
S0, and an external P-Channel to provide power from 5V
Standby (5VSB) in S3.
5. An internal LDO which regulates "3.3V Always" in S3
mode from VCC(VSB). In S3, this regulator is capable
of 1.25A peak currents with average currents limited by
the thermal design of the PCB.
At initial power-up, or when transitioning from S5, the PWM
regulator will be disabled until 5V MAIN is above its UVLO
threshold.
Table 2. ACPI States
STATE
S5
S3
S0
S3#I
X
L
H
EN (S5#)
L
H
H
S3#O
L
L
H
STATE
S5
S3
S0
SBSW
H
L
H
VDDQ
OFF
ON
ON
VTT
OFF
OFF
ON
3.3 ALW
LDO
LDO
Q5 (MAIN)
5V Dual
OFF
+5VSB
+5 MAIN
G1.2 LDO 3.3 ALW LDO
OFF
ON
OFF
ON
ON
OFF
8
REV. 1.0.1 9/9/04