FAN5068 Datasheet, PDF (13/18 Pages) Fairchild Semiconductor – DDR-1/DDR-2 plus ACPI Regulator Combo

FAN5068
PRODUCT SPECIFICATION
Over-Current Sensing
If the circuit's current limit signal (“ILIM det” as shown in
Figure 8) is high at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the next 8
clock cycles. If at any time from the 9^th to the 16^th clock
cycle, the “ILIM det” is again reached, the fault latch is set.
If “ILIM det” does not occur between cycle 9 and 16, normal
operation is restored and the over-current circuit resets itself.
This fault is prevented from setting the fault latch during
soft-start (SS < 1.3V).
1
IL
2
PGOOD
8 CLK
VOUT
SHUTDOWN
3
CH1 5.0V
CH3 2.0AΩ
CH2 100mV
M 10.0µs
Figure 11. Over-Current Protection Waveforms
OVP / HS Fault / FB short to GND detection:
A HS Fault is detected when there is more than 0.5V from
SW to PGND 350ns after LDRV reaches 4V (same time as
the current sampling time).
OVP Fault Detection occurs if FB > 115% VREF for 16
clock cycles.
During soft-start, the output voltage could potentially “run
away” if either the FB pin is shorted to GND or R1 is open.
This fault will be detected if the following condition persists
for more than 14 µs during soft-start.
1. VDDQ IN (PWM output voltage) > 1V and
2. FB < 100mV
Any of these 3 faults will set the fault latch. These 3 faults
can set the fault latch during the SS time (SS < 1.3V).
To ensure that FB pin open will not cause a destructive con-
dition, a 1µA current source ensures that the FB pin will be
high if open. This will cause the regulator to keep the output
low, and eventually result in an Under-voltage fault shut-
down (after PWM SS complete).
Over-Temperature Protection
The chip incorporates an over temperature protection circuit
that shuts the chip down when a die temperature of about
160°C is reached. Normal operation is restored at when the
die temperature falls below 125°C with internal Power On
Reset asserted, resulting in a full soft-start cycle. To accom-
plish this, the over-temperature comparator should discharge
the SS pin.
VTT Regulator Section (Figure 3)
The VTT regulator includes an internal resistor divider (50k
for each resistor) from the output of the PWM regulator. If
the REF IN pin is left open, the divider will produce a volt-
age that is 50% of VDDQ IN.
The VTT regulator is enabled when S3#I is HIGH and the
PWM regulator’s internal PGOOD signal is true. The VTT
regulator also includes its own PGOOD signal which is high
when VTT SNS > 90% of REF IN.
LDO Controller
The LDO controller is typically used to provide 1.2V for the
Front-side bus GTL termination. Drop-out voltage for this
regulator will depend on the RDS(ON) of the external
N-Channel MOSFET pass element that is selected. Gate
drive comes from VCC and can pull up to within 0.5V of
VCC line. With 1.2V output, the enhancement voltage for
the MOSFET is: VENH = 4.75 - 0.5 - 1.2 = 3.05V. There-
fore, a low enhancement voltage MOSFET should be used
for the pass element.
The LDO controller contains a soft-start circuit which limits
its output slew rate when it powers up. The LDO's output
voltage (V_1.2) is established with the following equation
(reference designators are from Figure 1.):
V_1.2
=
0.9
×


1
+
RR-----78-_
(9)
Design and Component Selection
Guidelines
The spreadsheet calculator, which is part of AN-6006 can be
used to calculate all external component values for the
FAN5068. As an initial step, define:
1. Output voltage
2. Maximum VDDQ load current
3. Maximum load transient current and maximum allow-
able output drop during load transient
4. RDS(ON) of the low-side MOSFET (Q2)
5. Maximum allowable output ripple
REV. 1.0.1 9/9/04
13