FAN5068 Datasheet, PDF (15/18 Pages) Fairchild Semiconductor – DDR-1/DDR-2 plus ACPI Regulator Combo

FAN5068
PRODUCT SPECIFICATION
Low-Side Losses
Q2, however, switches on or off with its parallel shottky
diode conducting, therefore V_DS ≈ 0.5V. Since P_SW is pro-
portional to V_DS, Q2’s switching losses are negligible and
we can select Q2 based on R_DS(ON) only.
Conduction losses for Q2 are given by:
P_COND = (1 – D) × I_OUT2 × R_DS(ON)
(13)
where R_DS(ON) is the R_DS(ON) of the MOSFET at the highest
operating junction temperature and
D = ^V-----O----^U----^T-
V_IN
is the minimum duty cycle for the converter. Since D_MIN <
20% for portable computers, (1-D) ≈ 1 produces a conserva-
tive result, further simplifying the calculation.
The maximum power dissipation (P_D(MAX)) is a function of
the maximum allowable die temperature of the low-side
MOSFET, the θ_J-A, and the maximum allowable ambient
temperature rise:
P_D(MAX) = ^T----J---⁽-^M-----^A----^X--_θ-⁾---_J^–--_–---T-_A---^A----⁽--^M----^A----^X---⁾
(14)
θ_J-A, depends primarily on the amount of PCB area that can
be devoted to heat sinking (see FSC app note AN-1029 for
SO-8 MOSFET thermal information).
PCB Design Guidelines:
Below is a summary of recommendations for PCB layout
when using MLP packages:
1. PCB lead finger pad should be designed 0.2-0.5mm
longer than the package terminal length for good fillet-
ing.
2. Non Solder Mask Defined (NSMD) pads are recom-
mended over SMD pads due to the tighter tolerance on
copper etching than solder masking.
3. For Good thermal performance it is recommended to use
4 layer PCB's with vias to effectively remove heat from
the device.
4. For a 5X5 die size, it is recommended to use 0.3-
0.33mm size holes in the middle.
5. Vias should be plugged to prevent voids being formed
between the exposed pad and PCB thermal pad due to
solder escaping by the capillary effect. This can be
avoided by tenting the via during the solder mask pro-
cess. The via solder mask diameter should be 100µm
larger than the via hole diameter.
PCB Layout General Guidelines
Switching converters, even during normal operation, pro-
duce short pulses of current which could cause substantial
ringing and be a source of EMI if layout constrains are not
observed.
There are two sets of critical components in a DC-DC con-
verter. The switching power components process large
amounts of energy at high rate and are noise generators. The
low power components responsible for bias and feedback
functions are sensitive to noise.
A multi-layer printed circuit board is recommended. Dedi-
cate one solid layer for a ground plane. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels.
Notice all the nodes that are subjected to high dV/dt voltage
swing such as SW, HDRV and LDRV, for example. All sur-
rounding circuitry will tend to couple the signals from these
nodes through stray capacitance. Do not oversize copper
traces connected to these nodes. Do not place traces con-
nected to the feedback components adjacent to these traces.
Keep the wiring traces from the IC to the MOSFET gate and
source as short as possible and capable of handling peak cur-
rents of 2A. Minimize the area within the gate-source path to
reduce stray inductance and eliminate parasitic ringing at the
gate.
Locate small critical components like the soft-start capacitor
and current sense resistors as close as possible to the respec-
tive pins of the IC.
Specific Layout recommendations
All component designators reference Figure 1. Layout exam-
ples refer to the FAN5068 EVAL board, available through
your Fairchild Semiconductor representative.
1. All currents flow in a closed path. All routing should
ensure that the currents are returned to their source of
origin by the shortest possible path without creating
unnecessary loops.
2. A Multi layer (4 layers or more) PCB facilitates the use
of a complete Ground layer which acts as very low
impedance return path for both the control and power
return currents. This ground plane will also increase the
noise immunity of the control circuit by providing a
shield against radiated disturbances. In the Eval board
layout Layer 2 is reserved for the GND plane.
3. VCC of the controller should be de-coupled with a
ceramic capacitor (C4) very close to the pin. If it is pos-
sible, the capacitor could be connected across the VCC
(#14) and the GND (#19) pins on top copper. Pin 19
should also connect to the GND plane with a via at the
pin. If a short top-copper connection for C4 is not possi-
ble the capacitor should be close to the VCC pin with
REV. 1.0.1 9/9/04
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