FAN5068 Datasheet, PDF (10/18 Pages) Fairchild Semiconductor – DDR-1/DDR-2 plus ACPI Regulator Combo

PRODUCT SPECIFICATION
FAN5068
5V SB
V(UVLO)
4V
3.8V
1V
VDDQ
3.3V LDO
T0
T1
T2
T3 T4 T5
Figure 6. Start-up Sequence into S0.
PWM Regulator
A PSPICE model and spreadsheet calculator are available for
the VDDQ PWM regulator to select external components
and verify loop stability. The topics covered below provide
the explanation behind the calculations in the spreadsheet.
Setting the output voltage
The output voltage of the PWM regulator can be set in the
range of 0.9V to 90% of its power input by an external resis-
tor divider.
The internal reference is 0.9V. The output is divided down by
an external voltage divider to the FB pin (for example, R1
and R2 in Figure 1). There is also a 1µA precision (±5%)
current sourced out of FB to ensure that if the pin is open,
VDDQ will remain low. The output voltage therefore is:
0----.-9---V--- ₌ ^V-----O_----U_----T_{----–----0---.--9---V--- + 1µA}
(3a)
R2
R1
To minimize noise pickup on this node, keep the resistor to
GND (R2) below 2k. We selected R2 at 1.82k and solved for
R1.
R1 = ^{R-----2----•}--0---⁽_{.--9V----–-}^O---^U-1---_µ^T----A–-----0---.-9----⁾ = 1.816k ≈ 1.82k
(3b)
The synchronous buck converter is optimized for 5V opera-
tion. The PWM modulator uses an average current mode
control for simplified feedback loop compensation.
Oscillator
The oscillator frequency is 300kHz. The internal PWM ramp
is reset on the rising clock edge.
PWM Soft Start
When the PWM regulator is enabled the circuit will wait
until the VDDQ IN pin is below 100mV to ensure that the
soft-start cycle does not begin with a large residual voltage
on the PWM regulator output.
When the PWM regulator is disabled, 50Ω is turned on from
VDDQ IN to PGND to discharge the output.
The voltage at the positive input of the error amplifier is
limited to V_CSS which is charged with a 50µA current
source. Once CSS has charged to 0.9V, the output voltage
will be in regulation.
The time it takes SS to reach 0.9V is:
T_0.9
=
-0---.-9-----^×----C-----^S---^S-
50
(4)
where T_0.9 is in ms if C_SS is in nF.
CSS charges another 400mV before the PWM regulator’s
latched faults are enabled. When CSS reaches 2.5V, the VTT
and 1.2V LDO will begin their soft-start ramps. After the
VTT and 1.2V LDO regulators are in regulation, PGOOD is
then allowed to go HIGH (open). UVLO on VCC will
discharge SS and reset the IC.
To prevent large duty cycles and high currents during the
beginning of the PWM soft-start, the input to the PWM com-
parator is also clamped by CSS. This clamping action has no
practical effect on operation of the circuit after CSS has
passed about 0.4V.
10
REV. 1.0.1 9/9/04