FAN5068 Datasheet, PDF (14/18 Pages) Fairchild Semiconductor – DDR-1/DDR-2 plus ACPI Regulator Combo

PRODUCT SPECIFICATION
FAN5068
Power MOSFET Selection
For a complete treatment of MOSFET selection and
efficiency calculations, see:
AN-6005: Synchronous buck MOSFET loss calculations
with Excel model.
Losses in a MOSFET are the sum of its switching (P_SW) and
conduction (P_COND) losses.
In typical applications, the FAN5068 converter’s output
voltage is low with respect to its input voltage, therefore the
Lower MOSFET (Q2) is conducting the full load current for
most of the cycle. Q2 should be therefore be selected to min-
imize conduction losses, thereby selecting a MOSFET with
low R_DS(ON).
In contrast, the high-side MOSFET (Q1) has a much shorter
duty cycle, and its conduction loss will therefore have less of
an impact. Q1, however, sees most of the switching losses,
so Q1’s primary selection criteria should be gate charge.
High-Side Losses:
Figure 12 shows a MOSFET's switching interval, with the
upper graph being the voltage and current on the Drain to
Source and the lower graph detailing V_GS vs. time with a
constant current charging the gate. The x-axis therefore is
also representative of gate charge (Q_G). C_ISS = C_GD + C_GS,
and it controls t1, t2, and t4 timing. C_GD receives the current
from the gate driver during t3 (as V_DS is falling). The gate
charge (Q_G) parameters on the lower graph are either
specified or can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
The driver’s impedance and C_ISS determine t2 while t3’s
period is controlled by the driver’s impedance and Q_GD.
Since most of t_S occurs when V_GS = V_SP we can use a
constant current assumption for the driver to simplify the
calculation of t_S:
V_DS
C_ISS
C _GD
C _ISS
I_D
V_SP
V_TH
V_GS
Q_GS
Q_GD
Q_G(SW)
t1
t2
t3
4.5V
t4
t5
Figure 12. Switching Losses and QG
5V
R_D
VIN
HDRV
SW
C _GD
R_GATE
G
C_GS
Figure 13. Drive Equivalent Circuit
These losses are given by:
P_UPPER = P_SW + P_COND
P_SW
=


V-----_D----S----×_-----I--L-
2
×
2
×
t_{S}
F_SW
P_COND
=


V---V--_{O---I-U-N---T-}
× I_OUT2 × R_DS(ON)
(10a)
(10b)
where:
P_UPPER is the upper MOSFET’s total losses, and P_SW and
P_COND are the switching and conduction losses for a given
MOSFET. R_DS(ON) is at the maximum junction temperature
(T_J). t_S is the switching period (rise or fall time) and is t2+t3
(Figure 12).
t_S
=
-Q-----^G----⁽--^S---^W----⁾-
I_DRIVER
≈
-----------------Q-----^G----⁽--^S---^W----⁾-----------------


-R----_D---_R--V--_I--_V^C----_E-C--_R---–-+----V-R---^S--_G-^P--_A----_T---_E- _
(11)
Most MOSFET vendors specify Q_GD and Q_GS. Q_G(SW) can
be determined as: Q_G(SW) = Q_GD + Q_GS – Q_TH where Q_TH
is the gate charge required to get the MOSFET to it’s thresh-
old (V_TH). For the high-side MOSFET, V_DS = VIN, which
can be as high as 20V in a typical portable application.
Care should also be taken to include the delivery of the
MOSFET's gate power (P_GATE) in calculating the power
dissipation required for the FAN5068:
P_GATE = Q_G × VCC × F_SW
(12)
where Q_G is the total gate charge to reach VCC.
14
REV. 1.0.1 9/9/04