FAN5068 Datasheet, PDF (4/18 Pages) Fairchild Semiconductor – DDR-1/DDR-2 plus ACPI Regulator Combo

PRODUCT SPECIFICATION
VDDQ IN
R9
REF IN
R10
VTT SNS
50K
EN
+
–
50K
S3
VDDQ IN
VTT OUT
PGND
Pin Configuration
Figure 3. VTT Regulator Block Diagram
FAN5068
G1.2 1
FB1.2 2
SBSW 3
5V MAIN 4
VTT SNS 5
VTT OUT 6
24 23 22 21 20 19
P1 = GND
18 EN
17 S3#I
16 S3#O
15 3.3 ALW
14 VCC
13 PGOOD
7 8 9 10 11 12
FAN5068MP 5x5 mm MLP-24 Package (θ_JA = 38°C/W, θ_JC = 1.4°C/W)*
Note: Connect P1 pad to GND.
Pin Definitions
Pin # Pin Name
1 G1.2
2 FB1.2
3 SBSW
4 5V MAIN
5 VTT SNS
6 VTT OUT
7 VDDQ IN
Pin Function Description
Gate Drive for the 1.2V LDO. Turned off (low) in S3 and S5 modes.
Feedback for the 1.2V LDO Output. Tie to a voltage higher than 0.9V to disable this
regulator.
Standby Switch. Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in
S3. Goes high in S0 and S5.
5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited.
VTT Remote Sense Input.
VTT Regulator Power Output.
VDDQ Input from PWM. Connect to PWM output voltage. This is the VTT Regulator power
input.
*Test method as per JEDEC Specification JESD51-5
4
REV. 1.0.1 9/9/04