FIN224AC_08 Datasheet, PDF (5/19 Pages) Fairchild Semiconductor – 22-Bit Bi-Directional Serializer/Deserializer

Control Logic Circuitry
The FIN224AC has the ability to be used as a 22-bit seri-
alizer or a 22-bit deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin program-
ming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serial-
izer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serial-
izer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generate the opposite
state signal on DIRO. For unidirectional operation the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-direc-
tional operation, the DIRI of the master device is driven
by the system and the DIRO signal of the master is used
to drive the DIRI of the slave device.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are serialized or deserialized.
DP[21:22] inputs to the serializer are transmitted to
DP[23:24] outputs on the deserializer.
Turn-Around Functionality
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGH-
impedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differ-
ential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS out-
puts are placed into a HIGH-impedance state, and LVC-
MOS inputs are driven to a valid level internally.
Additionally all internal circuitry is reset. The loss of
CKREF state is also enabled to ensure that the PLL only
powers-up if there is a valid CKREF signal.
In a typical application mode, signals of the device do not
change states other than between the desired frequency
range and the power-down mode. This allows for sys-
tem-level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selec-
tion signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2
signals that have their operating mode driven to a “logic
1” should be connected to a system-level power-down or
reset signal.
Table 1. Control Logic Circuitry
Mode
Number
S2
S1 DIRI
Description
0
0
0
x Power-Down Mode
0
1
1 22-Bit Serializer 2MHz to 5MHz CKREF
1
0
1
0 22-Bit Deserializer
1
0
1 22-Bit Serializer 5MHz to 15MHz CKREF
2
1
0
0 22-Bit Deserializer
1
1
1 22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data)
3
1
1
0 22-Bit Deserializer
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.5
5
www.fairchildsemi.com