FIN224AC_08 Datasheet, PDF (15/19 Pages) Fairchild Semiconductor – 22-Bit Bi-Directional Serializer/Deserializer

AC Loading and Waveforms (Continued)
CKREF
t_TPPLD0
CKS0
Note: CKREF Signal can be stopped either High or LOW
Figure 12. PLL Loss of Clock Disable Time
t_TPPLD1
S1 or S2
CKS0
Figure 13. PLL Power-Down Time
t_PLZ(HZ)
S1 or S2
t_PZL(ZH)
DS+,CKS0+
DS+,CKS0-
HIGHZ
Note: CKREF must be active and PLL must be stable
Figure 14. Serializer Enable and Disable Time
t_PLZ(HZ)
S1 or S2
t_PZL(ZH)
DP
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
Figure 15. Deserializer Enable and Disable Times
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.5
15
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