FIN224AC_08 Datasheet, PDF (12/19 Pages) Fairchild Semiconductor – 22-Bit Bi-Directional Serializer/Deserializer

AC Electrical Characteristics
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
Typical values are given for V_DD = 2.775V and T_A = 25°C. Positive current values refer to the current flowing into
device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless other-
wise specified (except ΔV_OD and V_OD).
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
Serializer Input Operating Conditions
t_TCP
CKREF Clock Period
(2MHz – 26MHz)
CKREF = STROBE
Figure 7.
S2=0 S1=1
S2=1 S1=0
S2=1 S1=1
200
66
38.46
500
200
ns
100.00
f_REF
t_CPWH
t_CPWL
t_CLKT
t_SPWH
CKREF Frequency Relative to
STROBE
CKREF Clock High Time
CKREF Clock Low Time
LVCMOS Input Transition Time
STROBE Pulse Width HIGH/LOW
CKREF does not =
STROBE
S2=0 S1=1
2.25 x
f_STROBE
0.2
0.5
MHz
T
0.2
0.5
T
Figure 9.
90.0
ns
Figure 9.
(Tx4)/26
(Tx22)/26 ns
S2=0 S1=1 52
130
f_MAX Maximum Serial Data Rate
CKREF x 26
S2=1 S1=0 130
S2=1 S1=1 260
390 Mb/s
676
t_STC
DP_(n) Setup to STROBE
t_HTC DP_(n) Hold to STROBE
Serializer AC Electrical Characteristics
DIRI = 1
2.5
ns
2.0
ns
t_TCCD
Transmitter Clock Input to Clock
Output Delay
t_SPOS CKSO Position Relative to DS^(3.)
PLL AC Electrical Characteristics
CKREF = STROBE
33a+1.5
-50
35a+6.5 ns
250
ps
t_TPLLS0
Serializer Phase Lock Loop
Stabilization Time
Figure 11.
200
µs
t_TPLLD0
t_TPLLD1
PLL Disable Time Loss of Clock
PLL Power-Down Time^(4.)
Deserializer Input Operating Conditions
Figure 12.
Figure 13.
30
µs
20
ns
t_{S_DS}
Serial Port Setup Time,
DS-to-CKSI^(5.)
1.4
ns
t_{H_DS}
Serial Port Hold Time,
DS-to-CKS^(5.)
-250
ps
Deserializer AC Electrical Characteristics
t_RCOP
t_RCOL
t_RCOH
Deserializer Clock Output
(CKP OUT) Period^(6.)
CKP OUT Low Time^(6.)
CKP OUT High Time
Figure 10.
(Rising Edge STROBE) Serializer
source STROBE = CKREF
Figure 10.
50
13a-3
13a-3
500
ns
13a+3 ns
13a+3 ns
t_PDV Data Valid to CKP LOW
(Rising Edge STROBE)
Figure 10.
8a-6
8a+1 ns
t_ROLH Output Rise Time (20% to 80%)
C_L = 8pF
Figure 7.
18
ns
t_ROHL Output Fall Time (20% to 80%)
C_L = 8pF
Figure 7.
18
ns
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.5
12
www.fairchildsemi.com